Digital Electronics
A comprehensive guide to digital electronics covering number systems, Boolean algebra, logic gates, combinational and sequential circuits, flip-flops, counters, registers, finite state machines, memories, ADC/DAC fundamentals, and digital logic design. Includes truth tables, circuit diagrams, solved problems, and interview-oriented concepts.
#Number Systems and Digital Fundamentals#
##Introduction to digital electronics#
A friendly, structured set of notes covering the basics and the more advanced ideas of Unit 1: Introduction to Digital Electronics. Read top to bottom the first time, then use the table of contents and summary tables for quick revision.
📑 Table of Contents
- Analog vs Digital Signals
- Characteristics of Digital Systems
- Binary Logic and Logic Levels
- Positive and Negative Logic
- Digital Waveforms and Pulse Terminology
- Digital System Advantages and Limitations
- Applications of Digital Electronics
- Basic Digital Circuit Symbols
- Introduction to Logic Families
- Quick Revision Cheat Sheet
1. Analog vs Digital Signals
1.1 What is a signal?
A signal is a physical quantity (usually voltage or current) that carries information and changes with time. Everything an electronic system senses, processes or transmits is a signal.
1.2 Analog signal
An analog signal is continuous in both time and amplitude. It can take any value within a range, and it changes smoothly.
- Between 2 V and 3 V there are infinitely many possible values (2.1 V, 2.55 V, 2.5501 V ...).
- Natural quantities are analog: temperature, sound, light intensity, pressure, speed.
- Example: the output of a microphone, a sine wave.
Voltage
^ ___
| / \ /\
| / \ / \
| / \______/ \___ <- smooth, continuous curve
+-------------------------------> Time
1.3 Digital signal
A digital signal is discrete. It can take only a limited set of values, usually just two: HIGH or LOW (1 or 0). It jumps between levels instead of varying smoothly.
Voltage
^ +-----+ +---+
| | | | |
| | | | |
| ----+ +-------+ +---- <- only two levels
+-------------------------------> Time
1 0 1 0
1.4 Comparison table
| Feature | Analog Signal | Digital Signal |
|---|---|---|
| Nature | Continuous | Discrete (step-like) |
| Values | Infinite possible values | Finite (normally 2: 0 and 1) |
| Representation | Continuous waveform (e.g. sine) | Square or pulse waveform |
| Noise immunity | Poor; noise changes the information | Good; small noise is ignored |
| Accuracy | Limited by noise and component drift | High; limited only by number of bits |
| Storage | Difficult, degrades over time | Easy, can be stored without loss |
| Processing | Amplifiers, filters (hardware) | Logic gates, processors |
| Power use | Generally higher | Generally lower |
| Circuit design | Often complex, tuned | Easy to design and automate |
| Examples | Vinyl record, analog watch, thermometer | CD, digital watch, computer |
1.5 Analog ↔ Digital conversion
Real-world quantities are analog, but processing is done digitally, so conversion is needed:
- ADC (Analog-to-Digital Converter): converts a continuous signal into binary numbers (e.g. microphone to digital audio).
- DAC (Digital-to-Analog Converter): converts binary numbers back into a continuous signal (e.g. digital audio to speaker).
Real world --> Sensor --> ADC --> Digital Processing --> DAC --> Output
(analog) (computer / logic)
1.6 Key idea
Analog = continuous, any value. Digital = discrete, only specific values (0 or 1).
2. Characteristics of Digital Systems
A digital system is a system that represents and processes information using discrete (usually binary) values.
2.1 Core characteristics
- Discrete values. Information is represented by distinct levels. Binary systems use only two (0 and 1).
- Binary number system. All data (numbers, text, images, sound) is converted to strings of bits.
- Noise immunity. Because only two levels matter, small disturbances do not change the meaning of a bit (explained in Section 3).
- High accuracy and precision. Precision increases by adding more bits (8-bit, 16-bit, 32-bit ...).
- Easy storage. Bits can be stored in flip-flops, registers, memories, and disks without degradation.
- Programmability. Behaviour can be changed by changing software or stored data, not hardware.
- Speed. Digital circuits switch in nanoseconds or faster.
- Reliability and repeatability. The same input always gives the same output.
- Integration (miniaturisation). Millions or billions of gates fit on a single chip (IC).
- Time-multiplexing. Several signals can share one communication path by taking turns.
2.2 Bit, byte and word
| Term | Meaning |
|---|---|
| Bit | One binary digit (0 or 1). The smallest unit of information |
| Nibble | 4 bits |
| Byte | 8 bits |
| Word | A group of bits a system processes together (8, 16, 32, 64 ...) |
2.3 Number of combinations
With n bits you can represent 2ⁿ different values.
| Bits (n) | Combinations (2ⁿ) |
|---|---|
| 1 | 2 |
| 2 | 4 |
| 3 | 8 |
| 4 | 16 |
| 8 | 256 |
2.4 Types of digital circuits (an overview)
- Combinational circuits: output depends only on the present inputs (e.g. gates, adders, multiplexers).
- Sequential circuits: output depends on present inputs and past history (memory) (e.g. flip-flops, counters, registers).
3. Binary Logic and Logic Levels
3.1 Binary logic
Binary logic deals with variables that can take only two values. These two values are given different names depending on context:
| Value A | Value B |
|---|---|
| 0 | 1 |
| LOW | HIGH |
| FALSE | TRUE |
| OFF | ON |
| NO | YES |
| Open switch | Closed switch |
Binary logic is built on three basic operations: AND, OR, NOT (symbols in Section 8).
3.2 Logic levels
A digital circuit does not use exact voltages for 0 and 1. It uses ranges of voltage, called logic levels.
For a typical 5 V TTL system:
5 V ---------------------------------
| |
| HIGH range (Logic 1) |
2.0 V |-------------------------------| <- V_IH(min)
| |
| FORBIDDEN / INDETERMINATE |
| (undefined region) |
0.8 V |-------------------------------| <- V_IL(max)
| LOW range (Logic 0) |
0 V ---------------------------------
- Voltages in the HIGH range are interpreted as logic 1.
- Voltages in the LOW range are interpreted as logic 0.
- Voltages in the forbidden (undefined) region give an unpredictable result and must be avoided (except for brief transitions).
3.3 Important voltage parameters
| Parameter | Meaning |
|---|---|
| V_IH(min) | Minimum input voltage accepted as HIGH |
| V_IL(max) | Maximum input voltage accepted as LOW |
| V_OH(min) | Minimum output voltage a device gives for HIGH |
| V_OL(max) | Maximum output voltage a device gives for LOW |
3.4 Typical values (standard TTL, 5 V)
| Parameter | Value |
|---|---|
| V_IL(max) | 0.8 V |
| V_IH(min) | 2.0 V |
| V_OL(max) | 0.4 V |
| V_OH(min) | 2.4 V |
3.5 Noise margin
Noise margin is the amount of unwanted voltage (noise) a circuit can tolerate without producing a wrong logic level. It is the "safety cushion" between what a device outputs and what the next device needs to see.
- High-level noise margin:
NM_H = V_OH(min) − V_IH(min) - Low-level noise margin:
NM_L = V_IL(max) − V_OL(max)
Example (standard TTL):
- NM_H = 2.4 − 2.0 = 0.4 V
- NM_L = 0.8 − 0.4 = 0.4 V
A larger noise margin means better noise immunity.
3.6 Why ranges matter
Because logic levels are ranges, the circuit still works even when the voltage is slightly off from ideal due to noise, temperature, or supply variation. This is the reason digital circuits are more reliable than analog circuits.
4. Positive and Negative Logic
The relationship between voltage level and logic value is a convention. Two conventions exist.
4.1 Positive logic
- HIGH (more positive) voltage = Logic 1
- LOW (less positive) voltage = Logic 0
This is the most commonly used convention.
4.2 Negative logic
- LOW voltage = Logic 1
- HIGH voltage = Logic 0
4.3 Side-by-side
| Voltage Level | Positive Logic | Negative Logic |
|---|---|---|
| HIGH (e.g. 5 V) | 1 | 0 |
| LOW (e.g. 0 V) | 0 | 1 |
4.4 Same circuit, different function
The same physical circuit performs a different logic function depending on the convention used.
Example: A circuit with this voltage behaviour (H = high, L = low):
| A | B | Output (voltage) |
|---|---|---|
| L | L | L |
| L | H | L |
| H | L | L |
| H | H | H |
- In positive logic (H = 1): output is 1 only when both inputs are 1 → it is an AND gate.
- In negative logic (L = 1): output is 1 when either input is 1 → it is an OR gate.
4.5 Gate conversion rule (duality)
| Gate in Positive Logic | Becomes in Negative Logic |
|---|---|
| AND | OR |
| OR | AND |
| NAND | NOR |
| NOR | NAND |
NOT gates and buffers remain NOT and buffer.
4.6 Remember
- Always state which logic convention is being used.
- Unless told otherwise, assume positive logic.
- Negative logic is often written with a bubble on the symbol or with an overbar (e.g. active-low signals like
RESET̅).
Active-HIGH: the signal is "active" (does its job) when HIGH. Active-LOW: the signal is "active" when LOW.
5. Digital Waveforms and Pulse Terminology
5.1 Digital waveforms
A digital waveform shows how a digital signal changes between HIGH and LOW levels over time. It is made of pulses and transitions. A diagram showing several waveforms against time is called a timing diagram.
5.2 Pulse
A pulse is a rapid change from one level to another and back again.
Positive-going pulse: goes from LOW to HIGH, stays, then returns to LOW.
+-----+
| |
------+ +------
rising falling
edge edge
Negative-going pulse: goes from HIGH to LOW, stays, then returns to HIGH.
------+ +------
| |
+-----+
falling rising
edge edge
5.3 Edges
- Rising edge (leading edge / positive edge): the transition from LOW to HIGH.
- Falling edge (trailing edge / negative edge): the transition from HIGH to LOW.
For a positive pulse, the leading edge is the rising edge. For a negative pulse, the leading edge is the falling edge.
5.4 Ideal vs. practical (real) pulse
- Ideal pulse: transitions are instantaneous, perfectly vertical and flat-topped.
- Practical pulse: takes finite time to rise and fall, and has imperfections.
Practical pulse (labels):
100% .......... ___overshoot__
/ \
90% ....... / \ <--- droop on top
/ \
50% .......+---- t_w ------------+.....
/ \
10% ..... / \
0% ______/<-t_r-> <-t_f->\______
5.5 Pulse terminology
| Term | Symbol | Meaning |
|---|---|---|
| Rise time | t_r | Time for the pulse to go from 10% to 90% of its amplitude |
| Fall time | t_f | Time for the pulse to go from 90% to 10% of its amplitude |
| Pulse width | t_w | Time between the 50% points of the rising and falling edges |
| Amplitude | V | Height of the pulse (difference between HIGH and LOW levels) |
| Overshoot | Peak that goes above the final HIGH level after the rising edge | |
| Undershoot | Dip that goes below the final LOW level after the falling edge | |
| Ringing | Oscillation (damped wiggle) after a sharp transition | |
| Droop (sag) | Slow decrease in the top of the pulse | |
| Propagation delay | t_p | Time between an input change and the resulting output change |
5.6 Periodic and non-periodic waveforms
- Periodic waveform: repeats itself at fixed time intervals (e.g. a clock).
- Non-periodic waveform: does not repeat in a regular pattern (e.g. data bits).
5.7 Period, frequency and duty cycle (for periodic waveforms)
- Period (T): the time for one complete cycle.
- Frequency (f): the number of cycles per second, measured in hertz (Hz).
f = 1 / T T = 1 / f
- Duty cycle: the fraction (or percentage) of the period during which the signal is HIGH.
Duty cycle (%) = ( t_w / T ) × 100
Example: A clock has t_w = 2 µs and T = 10 µs.
- f = 1 / 10 µs = 100 kHz
- Duty cycle = (2 / 10) × 100 = 20%
A 50% duty cycle gives a perfect square wave (equal HIGH and LOW time).
5.8 Clock signal
A clock is a periodic digital waveform used to synchronise operations in a digital system. All sequential circuits change state in step with the clock edges.
5.9 Timing diagram example
Clock : _|‾|_|‾|_|‾|_|‾|_
A : ____|‾‾‾‾‾‾‾|_____
B : ‾‾‾‾‾‾|_________
Timing diagrams show which signals are HIGH or LOW at each instant and how they relate to the clock.
5.10 Serial and parallel data (in terms of waveforms)
- Serial transmission: bits are sent one after another on a single line, over time.
- Parallel transmission: several bits are sent at the same time on multiple lines.
6. Digital System Advantages and Limitations
6.1 ✅ Advantages
| # | Advantage | Explanation |
|---|---|---|
| 1 | Noise immunity | Small noise does not change the 0 or 1 interpretation |
| 2 | Accuracy and precision | More bits = more precision; results are exactly reproducible |
| 3 | Easy storage | Information is stored in memory with no degradation |
| 4 | Programmability | Function can be changed by software without changing hardware |
| 5 | Easy design | Circuits are made from simple repeated building blocks (gates) |
| 6 | Integration | Huge numbers of gates fit on one chip; low cost per function |
| 7 | Low power (generally) | Switching circuits dissipate less power than continuously biased analog stages |
| 8 | Error detection and correction | Parity, checksums, and error-correcting codes can detect and fix errors |
| 9 | Data security | Easy to encrypt and compress digital data |
| 10 | Reliability | Fewer components drift or age in ways that change behaviour |
| 11 | Multiplexing | Many signals can share one channel |
| 12 | Perfect copying | Copies are identical to the original |
6.2 ❌ Limitations
| # | Limitation | Explanation |
|---|---|---|
| 1 | Real world is analog | Needs ADC and DAC, which add cost, complexity and delay |
| 2 | Quantisation error | Continuous values are rounded to the nearest level when digitised |
| 3 | Sampling limits | Signal must be sampled fast enough (at least twice the highest frequency) or information is lost |
| 4 | Bandwidth requirement | Digital transmission often needs more bandwidth than the equivalent analog signal |
| 5 | Speed limited by conversion | Very high-frequency signals can be hard to convert in real time |
| 6 | Power at high speed | Dynamic power increases with switching frequency |
| 7 | Power-hungry for some tasks | Processing small analog signals digitally can use more circuitry than a simple analog stage |
| 8 | Synchronisation required | Clock distribution and timing must be managed carefully |
| 9 | Complexity of design for large systems | Needs design tools and verification |
6.3 Takeaway
The advantages outweigh the limitations in most applications. That is why digital technology dominates modern electronics, while analog circuits remain necessary at the "edges" (sensors, amplifiers, power, radio-frequency front ends).
7. Applications of Digital Electronics
Digital electronics is found almost everywhere.
7.1 Computing
- Microprocessors and microcontrollers
- Computers, laptops, servers
- Memory devices (RAM, ROM, flash)
- Calculators
7.2 Communication
- Mobile phones and cellular networks
- Internet, routers, modems
- Digital television and radio broadcasting
- Satellite communication
- Optical fibre links
7.3 Consumer electronics
- Digital watches and clocks
- Digital cameras
- Smart TVs, audio players, gaming consoles
- Home appliances (washing machines, microwave ovens, air conditioners)
- Wearables and smart-home devices
7.4 Industrial and control
- Programmable logic controllers (PLCs)
- Robotics and automation
- Process control and motor control
- Digital instrumentation (digital multimeters, oscilloscopes)
7.5 Automotive
- Engine control units (ECU)
- Anti-lock braking (ABS), airbags
- Infotainment and navigation systems
7.6 Medical
- Digital thermometers and BP monitors
- ECG and EEG machines
- CT and MRI scanners
- Pacemakers and patient monitors
7.7 Aerospace and defence
- Flight control systems and avionics
- Radar and navigation (GPS)
- Missile guidance
7.8 Other everyday uses
- Traffic-light controllers
- ATMs, barcode scanners, electronic voting machines
- Digital displays (seven-segment, LCD, LED)
- Security systems and access control
7.9 Example: the building blocks used
| Application | Typical digital blocks involved |
|---|---|
| Digital clock | Counters, decoders, seven-segment display |
| Calculator | Adders, registers, encoders |
| Traffic light | Counters, flip-flops, timers |
| Computer | Gates, flip-flops, memory, ALU |
8. Basic Digital Circuit Symbols
Digital circuits are drawn using logic gate symbols. A logic gate is the basic building block that performs a logical operation on one or more binary inputs and gives one binary output.
A small circle (bubble) at an input or output means inversion (NOT).
8.1 NOT gate (Inverter)
- One input, one output.
- Output is the complement of the input.
- Symbol: triangle with a bubble at the output.
- Expression: Y = A̅ (written
Y = A'orY = ¬A)
| A | Y |
|---|---|
| 0 | 1 |
| 1 | 0 |
A ----|>o---- Y
8.2 Buffer
- One input, one output; output is the same as the input.
- Used to strengthen (amplify) the signal or isolate stages.
- Symbol: triangle without a bubble.
- Expression: Y = A
A ----|>---- Y
8.3 AND gate
- Output is 1 only if all inputs are 1.
- Symbol: flat back, rounded front (D-shape).
- Expression: Y = A · B
| A | B | Y |
|---|---|---|
| 0 | 0 | 0 |
| 0 | 1 | 0 |
| 1 | 0 | 0 |
| 1 | 1 | 1 |
A ---|‾‾\
| )--- Y
B ---|__/
8.4 OR gate
- Output is 1 if at least one input is 1.
- Symbol: curved back, pointed front (shield shape).
- Expression: Y = A + B
| A | B | Y |
|---|---|---|
| 0 | 0 | 0 |
| 0 | 1 | 1 |
| 1 | 0 | 1 |
| 1 | 1 | 1 |
8.5 NAND gate (NOT-AND)
- AND followed by NOT. Output is 0 only if all inputs are 1.
- Symbol: AND shape with a bubble at the output.
- Expression: Y = (A · B)'
| A | B | Y |
|---|---|---|
| 0 | 0 | 1 |
| 0 | 1 | 1 |
| 1 | 0 | 1 |
| 1 | 1 | 0 |
8.6 NOR gate (NOT-OR)
- OR followed by NOT. Output is 1 only if all inputs are 0.
- Symbol: OR shape with a bubble at the output.
- Expression: Y = (A + B)'
| A | B | Y |
|---|---|---|
| 0 | 0 | 1 |
| 0 | 1 | 0 |
| 1 | 0 | 0 |
| 1 | 1 | 0 |
8.7 XOR gate (Exclusive-OR)
- Output is 1 when the inputs are different (odd number of 1s).
- Symbol: OR shape with an extra curved line at the input side.
- Expression: Y = A ⊕ B = A'B + AB'
| A | B | Y |
|---|---|---|
| 0 | 0 | 0 |
| 0 | 1 | 1 |
| 1 | 0 | 1 |
| 1 | 1 | 0 |
8.8 XNOR gate (Exclusive-NOR)
- Output is 1 when the inputs are the same.
- Symbol: XOR shape with a bubble at the output.
- Expression: Y = (A ⊕ B)' = AB + A'B'
| A | B | Y |
|---|---|---|
| 0 | 0 | 1 |
| 0 | 1 | 0 |
| 1 | 0 | 0 |
| 1 | 1 | 1 |
8.9 Summary table of gates
| Gate | Symbol shape | Boolean expression | Output is 1 when ... |
|---|---|---|---|
| NOT | Triangle + bubble | A' | input is 0 |
| Buffer | Triangle | A | input is 1 |
| AND | D-shape | A·B | all inputs are 1 |
| OR | Curved shield | A+B | any input is 1 |
| NAND | D-shape + bubble | (A·B)' | any input is 0 |
| NOR | Shield + bubble | (A+B)' | all inputs are 0 |
| XOR | Shield + extra curve | A⊕B | inputs differ |
| XNOR | XOR + bubble | (A⊕B)' | inputs are equal |
8.10 Universal gates
NAND and NOR are called universal gates because any logic function (AND, OR, NOT, etc.) can be built using only NAND gates or only NOR gates.
8.11 Multi-input gates
AND, OR, NAND, NOR (and XOR/XNOR) can have more than two inputs. The number of input combinations is 2ⁿ for n inputs (3 inputs = 8 rows in the truth table).
8.12 Other common block symbols
Beyond gates, digital diagrams also use block symbols (rectangles with labelled pins) for:
- Flip-flops (inputs such as D, CLK, Q, Q̅)
- Multiplexers, decoders, encoders
- Counters and registers
A small triangle (>) at a clock input marks it as edge-triggered. A bubble on an input marks it active-LOW.
9. Introduction to Logic Families
9.1 What is a logic family?
A logic family is a group of digital integrated circuits that:
- are built using the same circuit technology (same type of transistors and design style), and
- have compatible electrical characteristics (voltage levels, supply, speed), so they can be connected together directly.
9.2 Classification
Logic Families
|
+------------------+------------------+
| | |
Bipolar Unipolar BiCMOS
(BJT-based) (MOS-based) (BJT + CMOS combined)
| |
+-----+-----+ +-----+-----+
| | | | | |
Saturated Non- PMOS NMOS CMOS
(RTL, DTL, saturated
TTL, I²L) (ECL)
| Category | Families | Basic device |
|---|---|---|
| Bipolar (saturated) | RTL, DTL, TTL, I²L | BJT in saturation |
| Bipolar (non-saturated) | ECL | BJT kept out of saturation (faster) |
| Unipolar (MOS) | PMOS, NMOS, CMOS | MOSFET |
| Combined | BiCMOS | BJT + CMOS |
Short forms: RTL = Resistor-Transistor Logic, DTL = Diode-Transistor Logic, TTL = Transistor-Transistor Logic, ECL = Emitter-Coupled Logic, I²L = Integrated-Injection Logic, CMOS = Complementary MOS.
9.3 Characteristics used to compare logic families
| Parameter | Meaning |
|---|---|
| Propagation delay (t_pd) | Time taken for a change at the input to appear at the output. Smaller = faster |
| Power dissipation | Power consumed by a gate (mW or µW). Lower is better |
| Speed-power product | Propagation delay × power dissipation (in picojoules). A figure of merit; lower is better |
| Fan-in | Maximum number of inputs a gate can have |
| Fan-out | Maximum number of similar gate inputs one gate output can drive reliably |
| Noise margin | Tolerance to unwanted noise (see Section 3.5). Higher is better |
| Supply voltage (V_CC / V_DD) | Voltage needed to power the IC |
| Logic levels | The V_IH, V_IL, V_OH, V_OL values |
| Operating temperature range | Range over which the IC works correctly (commercial vs military) |
| Cost and availability | Practical selection factors |
Fan-out example: If a gate can supply 10 mA when HIGH and each load needs 1 mA, then fan-out = 10.
9.4 Brief on important families
🔹 TTL (Transistor-Transistor Logic)
- Built with bipolar junction transistors (BJTs).
- Supply: +5 V.
- Popular 7400 series (commercial, 0 °C to 70 °C) and 5400 series (military, −55 °C to 125 °C).
- Typical gate delay: ~10 ns (standard TTL); fan-out about 10.
- Output stage is often a totem-pole arrangement.
- Unused inputs left open usually behave as logic 1.
- Sub-series: 74 (standard), 74L (low power), 74H (high speed), 74S (Schottky), 74LS (low-power Schottky), 74AS, 74ALS, 74F.
🔹 ECL (Emitter-Coupled Logic)
- BJTs operate in non-saturation mode, which removes storage delay.
- Fastest family (sub-nanosecond delays).
- Drawbacks: high power dissipation, low noise margin, unusual logic levels (about −0.9 V for HIGH and −1.7 V for LOW, using negative supply).
- Used in very high-speed applications.
🔹 MOS Families (PMOS, NMOS)
- Use MOSFETs; very compact, allow high packing density.
- Lower power than bipolar but slower.
- Largely replaced by CMOS.
🔹 CMOS (Complementary MOS)
- Uses both P-channel and N-channel MOSFETs in complementary pairs.
- Very low static power consumption (power mainly used only while switching).
- High noise margin (about 30–45% of supply voltage).
- Wide supply range (e.g. 3 V to 15 V for the original 4000 series).
- High fan-out (because of very high input impedance).
- Disadvantages: sensitive to static electricity, power grows with switching frequency, historically slower than TTL.
- Unused inputs must not be left floating; connect them to supply or ground.
- Series: 4000/4500 series, 74HC, 74HCT (TTL-compatible inputs), 74AC, 74ACT, etc.
🔹 BiCMOS
- Combines the high speed and drive of bipolar with the low power and high density of CMOS.
9.5 Comparison: TTL vs CMOS vs ECL
| Feature | TTL (74LS) | CMOS (4000 / 74HC) | ECL |
|---|---|---|---|
| Basic device | BJT | MOSFET (P+N) | BJT (non-saturated) |
| Supply voltage | 5 V (±5%) | 3–15 V (4000), 2–6 V (74HC) | −5.2 V |
| Propagation delay | ~10 ns | ~10–100 ns (4000), ~8 ns (74HC) | < 1 ns |
| Power per gate | ~2 mW (LS) | ~µW (static) | ~25–60 mW |
| Noise margin | Moderate (≈0.4 V) | High (≈30–45% of V_DD) | Low (≈0.2 V) |
| Fan-out | ~10 | > 50 (very high) | ~25 |
| Packing density | Medium | Very high | Low |
| Static sensitivity | Low | High | Low |
| Main use | General purpose | Low-power, battery, VLSI | Ultra-high-speed |
(Values are typical and vary by series and manufacturer.)
9.6 Open-collector / open-drain outputs
- Some gates have an open-collector (TTL) or open-drain (CMOS) output with no internal pull-up.
- An external pull-up resistor is required.
- Allows outputs to be wired together (wired-AND), and helps interface between different voltage levels.
9.7 Three-state (tri-state) outputs
- Output can be HIGH, LOW, or high-impedance (Hi-Z), which behaves as if disconnected.
- Allows many devices to share a common bus safely, with only one driving at a time.
9.8 Interfacing between families
When connecting different families, check that:
- The driver's V_OH(min) ≥ the receiver's V_IH(min),
- The driver's V_OL(max) ≤ the receiver's V_IL(max),
- The driver can supply/absorb the current the receiver needs.
If not, use a level shifter, a pull-up resistor, or a compatible variant (e.g. 74HCT for TTL-to-CMOS).
9.9 Choosing a logic family
| If you need ... | Prefer |
|---|---|
| Lowest power / battery operation | CMOS |
| Highest speed | ECL (or fast BiCMOS/advanced CMOS) |
| Good all-round, easy to use | TTL / 74HC |
| High noise environment | CMOS |
| Dense integration (VLSI) | CMOS |
📝 Quick Revision Cheat Sheet
| Topic | Remember this |
|---|---|
| Analog vs Digital | Analog = continuous; Digital = discrete (0/1) |
| Bits | n bits → 2ⁿ combinations |
| Logic levels | Voltage ranges for 0 and 1, with a forbidden region between |
| Noise margin | NM_H = V_OH − V_IH; NM_L = V_IL − V_OL |
| Positive logic | HIGH = 1, LOW = 0 (default) |
| Negative logic | LOW = 1, HIGH = 0; AND ↔ OR, NAND ↔ NOR |
| Rise / fall time | 10%–90% / 90%–10% of amplitude |
| Pulse width | Measured between 50% points |
| Frequency | f = 1/T |
| Duty cycle | (t_w / T) × 100% |
| Advantage (top) | Noise immunity, easy storage, programmability |
| Limitation (top) | Needs ADC/DAC; quantisation error |
| Universal gates | NAND and NOR |
| Bubble | Inversion / active-LOW |
| Logic family | Group of ICs with same technology and compatible levels |
| Fastest family | ECL |
| Lowest power family | CMOS |
| Most common general family | TTL (7400) and 74HC |
| Fan-out | How many gate inputs one output can drive |
| Speed-power product | Delay × power (lower is better) |
🧠 Practice Questions
- Differentiate between analog and digital signals with two examples each.
- List any five characteristics of a digital system.
- A gate has V_OH(min) = 2.4 V, V_IH(min) = 2.0 V, V_IL(max) = 0.8 V, V_OL(max) = 0.4 V. Find both noise margins.
- A circuit works as an AND gate in positive logic. What does it work as in negative logic?
- A clock has a period of 20 µs and HIGH time of 5 µs. Find the frequency and duty cycle.
- Define rise time, fall time and pulse width.
- State any four advantages and four limitations of digital systems.
- Name five applications of digital electronics.
- Draw the symbol and truth table of NAND and XOR gates.
- What is a logic family? Define fan-out, propagation delay and speed-power product.
- Compare TTL and CMOS logic families.
Click for answers to the numerical questions
- Q3: NM_H = 2.4 − 2.0 = 0.4 V; NM_L = 0.8 − 0.4 = 0.4 V.
- Q4: It works as an OR gate.
- Q5: f = 1 / 20 µs = 50 kHz; Duty cycle = (5 / 20) × 100 = 25%.
##Number Systems and Conversions#
Friendly, structured notes for Unit 2: Number Systems and Conversions. Start from the top if you are new. Use the tables and the cheat sheet at the end for quick revision.
📑 Table of Contents
- Decimal Number System
- Binary Number System
- Octal Number System
- Hexadecimal Number System
- Conversions Between Number Systems
- Binary Fractions and Fractional Conversions
- Radix and Positional Notation
- BCD (Binary-Coded Decimal)
- 8421, 2421 and Other Weighted Codes
- Excess-3 Code
- Gray Code and Binary-to-Gray Conversion
- Alphanumeric Codes: ASCII and Unicode
- Quick Revision Cheat Sheet
🧭 Big Picture
A number system is a way of writing numbers using a fixed set of symbols (digits). The number of different digits it uses is called its base or radix.
| System | Base (Radix) | Digits used |
|---|---|---|
| Decimal | 10 | 0 1 2 3 4 5 6 7 8 9 |
| Binary | 2 | 0 1 |
| Octal | 8 | 0 1 2 3 4 5 6 7 |
| Hexadecimal | 16 | 0–9 and A B C D E F |
Humans prefer decimal. Digital circuits work in binary. Octal and hexadecimal are compact shorthands for long binary strings. Codes such as BCD, Gray and ASCII are special ways of representing decimal digits or characters in binary.
1. Decimal Number System
- Base 10, with 10 digits:
0 to 9. - It is the number system we use in daily life.
- It is a positional system: the value of a digit depends on its position.
1.1 Place values
Each position is a power of 10.
Position: 3 2 1 0 . -1 -2
Weight: 10³ 10² 10¹ 10⁰ 10⁻¹ 10⁻²
1000 100 10 1 0.1 0.01
1.2 Example
2745.63
2745.63 = 2×10³ + 7×10² + 4×10¹ + 5×10⁰ + 6×10⁻¹ + 3×10⁻²
= 2000 + 700 + 40 + 5 + 0.6 + 0.03
1.3 Key terms
- MSD (Most Significant Digit): leftmost digit, carries the highest weight.
- LSD (Least Significant Digit): rightmost digit, carries the lowest weight.
- Decimal point: separates the integer part from the fractional part.
2. Binary Number System
- Base 2, with only two digits:
0and1. - Each binary digit is called a bit (binary digit).
- It matches digital hardware perfectly: two voltage levels, HIGH (1) and LOW (0).
2.1 Place values (weights are powers of 2)
Position: 7 6 5 4 3 2 1 0
Weight: 128 64 32 16 8 4 2 1
2.2 Key terms
- MSB (Most Significant Bit): leftmost bit, highest weight.
- LSB (Least Significant Bit): rightmost bit, lowest weight.
- Nibble = 4 bits, Byte = 8 bits.
2.3 Range with n bits
- Number of different values: 2ⁿ
- Largest unsigned value: 2ⁿ − 1
| Bits | Values | Max unsigned number |
|---|---|---|
| 4 | 16 | 15 |
| 8 | 256 | 255 |
| 16 | 65,536 | 65,535 |
2.4 Binary to decimal (quick view)
1011₂ = 1×8 + 0×4 + 1×2 + 1×1 = 11₁₀
2.5 Counting table (0 to 15), with octal and hex
| Decimal | Binary | Octal | Hex |
|---|---|---|---|
| 0 | 0000 | 0 | 0 |
| 1 | 0001 | 1 | 1 |
| 2 | 0010 | 2 | 2 |
| 3 | 0011 | 3 | 3 |
| 4 | 0100 | 4 | 4 |
| 5 | 0101 | 5 | 5 |
| 6 | 0110 | 6 | 6 |
| 7 | 0111 | 7 | 7 |
| 8 | 1000 | 10 | 8 |
| 9 | 1001 | 11 | 9 |
| 10 | 1010 | 12 | A |
| 11 | 1011 | 13 | B |
| 12 | 1100 | 14 | C |
| 13 | 1101 | 15 | D |
| 14 | 1110 | 16 | E |
| 15 | 1111 | 17 | F |
💡 Memorise this table. It makes every conversion in this unit faster.
2.6 Why binary is hard for humans
1101011100101011 is long and easy to misread, which is why we group bits into octal or hex.
3. Octal Number System
- Base 8, with digits
0 to 7. (8 and 9 do not exist in octal.) - One octal digit = exactly 3 binary bits, since 2³ = 8.
3.1 Place values
Position: 3 2 1 0 . -1 -2
Weight: 512 64 8 1 1/8 1/64
3.2 Binary-octal equivalents
| Octal | 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 |
|---|---|---|---|---|---|---|---|---|
| Binary | 000 | 001 | 010 | 011 | 100 | 101 | 110 | 111 |
3.3 Example
(354)₈ = 3×64 + 5×8 + 4×1 = 192 + 40 + 4 = 236₁₀
3.4 Why use octal?
It shortens binary numbers by a factor of 3 and is easy to convert by simple grouping.
4. Hexadecimal Number System
- Base 16, with 16 symbols:
0 1 2 3 4 5 6 7 8 9 A B C D E F. - Letters stand for values above 9.
- One hex digit = exactly 4 binary bits, since 2⁴ = 16.
4.1 Letter values
| Hex | A | B | C | D | E | F |
|---|---|---|---|---|---|---|
| Decimal | 10 | 11 | 12 | 13 | 14 | 15 |
4.2 Place values
Position: 3 2 1 0 . -1 -2
Weight: 4096 256 16 1 1/16 1/256
4.3 Example
(3A7)₁₆ = 3×256 + 10×16 + 7×1 = 768 + 160 + 7 = 935₁₀
4.4 Why use hex?
- Very compact: 1 byte = 2 hex digits (e.g.
11010111₂ = D7₁₆). - Widely used for memory addresses, machine code, colour codes (e.g.
#FF5733), and debugging.
4.5 Common notations
Hex numbers are often written as 0x3A7, 3A7h or (3A7)₁₆.
5. Conversions Between Number Systems
There are 12 possible conversions among the four systems. They fall into a few simple methods.
┌───────────────┐
Method A │ DECIMAL │ Method B
(multiply & └───────┬───────┘ (repeated division
add) │ by the base)
┌────────────────┼────────────────┐
▼ ▼ ▼
BINARY ◄──────► OCTAL HEXADECIMAL
▲ (group 3 bits) ▲
└───────────(group 4 bits)────────┘
🅰️ Method A: Any base → Decimal (multiply by weights and add)
Binary → Decimal
101101₂ = 1×32 + 0×16 + 1×8 + 1×4 + 0×2 + 1×1 = 32 + 8 + 4 + 1 = 45₁₀
Octal → Decimal
(725)₈ = 7×64 + 2×8 + 5×1 = 448 + 16 + 5 = 469₁₀
Hex → Decimal
(2F9)₁₆ = 2×256 + 15×16 + 9×1 = 512 + 240 + 9 = 761₁₀
🅱️ Method B: Decimal → Any base (repeated division)
Steps
- Divide the decimal number by the target base.
- Write down the remainder.
- Divide the quotient again. Repeat until the quotient is 0.
- Read the remainders from bottom to top (last remainder = MSB).
Decimal → Binary: 45
| Division | Quotient | Remainder |
|---|---|---|
| 45 ÷ 2 | 22 | 1 (LSB) |
| 22 ÷ 2 | 11 | 0 |
| 11 ÷ 2 | 5 | 1 |
| 5 ÷ 2 | 2 | 1 |
| 2 ÷ 2 | 1 | 0 |
| 1 ÷ 2 | 0 | 1 (MSB) |
Read upward: 45₁₀ = 101101₂ ✅
Decimal → Octal: 156
| Division | Quotient | Remainder |
|---|---|---|
| 156 ÷ 8 | 19 | 4 |
| 19 ÷ 8 | 2 | 3 |
| 2 ÷ 8 | 0 | 2 |
Read upward: 156₁₀ = (234)₈ ✅ (check: 2×64 + 3×8 + 4 = 156)
Decimal → Hexadecimal: 500
| Division | Quotient | Remainder |
|---|---|---|
| 500 ÷ 16 | 31 | 4 |
| 31 ÷ 16 | 1 | 15 = F |
| 1 ÷ 16 | 0 | 1 |
Read upward: 500₁₀ = (1F4)₁₆ ✅ (check: 256 + 240 + 4 = 500)
🅲 Method C: Binary ↔ Octal (group of 3 bits)
Binary → Octal: Group bits in threes starting from the right (pad with leading zeros on the left if needed), then replace each group with its octal digit.
1101011₂ → 001 | 101 | 011 → 1 5 3 → (153)₈
(check: 107₁₀ in both ✅)
Octal → Binary: Replace each octal digit with its 3-bit binary code.
(725)₈ → 7=111, 2=010, 5=101 → 111010101₂
🅳 Method D: Binary ↔ Hexadecimal (group of 4 bits)
Binary → Hex: Group in fours from the right (pad on the left), then replace each group by its hex digit.
11010111₂ → 1101 | 0111 → D 7 → (D7)₁₆
Hex → Binary: Replace each hex digit with its 4-bit code.
(2F9)₁₆ → 2=0010, F=1111, 9=1001 → 001011111001₂
🅴 Method E: Octal ↔ Hexadecimal (go through binary)
There is no direct shortcut. Use binary as the bridge.
Octal → Hex: (725)₈ → 111 010 101 → regroup in 4s: 0001 1101 0101 → (1D5)₁₆
(check: both = 469₁₀ ✅)
Hex → Octal: (2F9)₁₆ → 0010 1111 1001 → regroup in 3s: 001 011 111 001 → (1371)₈
(check: both = 761₁₀ ✅)
5.1 Summary table of methods
| From → To | Best method |
|---|---|
| Binary / Octal / Hex → Decimal | Multiply digits by weights and add |
| Decimal → Binary / Octal / Hex | Repeated division, read remainders upward |
| Binary ↔ Octal | Group of 3 bits |
| Binary ↔ Hex | Group of 4 bits |
| Octal ↔ Hex | Convert via binary |
5.2 Handy trick: the "sum of weights" method (Decimal → Binary)
Write the binary weights and tick the ones that add up to the number.
45 = 32 + 8 + 4 + 1 → weights 32, 8, 4, 1 are ON:
Weight: 32 16 8 4 2 1
Bit: 1 0 1 1 0 1 → 101101
6. Binary Fractions and Fractional Conversions
Numbers can have a radix point (binary point in binary). The digits to the right represent negative powers of the base.
6.1 Binary fraction weights
Position: ... 2 1 0 . -1 -2 -3 -4
Weight: ... 4 2 1 0.5 0.25 0.125 0.0625
(1/2) (1/4) (1/8) (1/16)
6.2 Binary fraction → Decimal
Multiply each bit by its weight and add.
101.011₂ = 1×4 + 0×2 + 1×1 + 0×0.5 + 1×0.25 + 1×0.125 = 5.375₁₀
6.3 Decimal fraction → Binary (repeated multiplication by 2)
Steps (for the fractional part only)
- Multiply the fraction by 2.
- The integer part (0 or 1) of the result is the next bit.
- Take the remaining fraction and multiply by 2 again.
- Stop when the fraction becomes 0 (or after enough bits for the required accuracy).
- Read the bits from top to bottom (first bit = most significant fractional bit).
Example: 0.625 → binary
| Step | Multiply | Result | Bit |
|---|---|---|---|
| 1 | 0.625 × 2 | 1.25 | 1 |
| 2 | 0.25 × 2 | 0.50 | 0 |
| 3 | 0.5 × 2 | 1.00 | 1 |
0.625₁₀ = 0.101₂ ✅ (0.5 + 0.125 = 0.625)
6.4 Mixed numbers (integer + fraction)
Convert the two parts separately, then join them with the point.
Example: 13.6875 → binary
- Integer: 13 →
1101 - Fraction: 0.6875 × 2 = 1.375 → 1; 0.375 × 2 = 0.75 → 0; 0.75 × 2 = 1.5 → 1; 0.5 × 2 = 1.0 → 1
- Fraction =
.1011
13.6875₁₀ = 1101.1011₂ ✅
6.5 Non-terminating (repeating) fractions
Some decimal fractions never end in binary, just like 1/3 = 0.333... in decimal.
Example: 0.1₁₀
| Multiply | Result | Bit |
|---|---|---|
| 0.1 × 2 | 0.2 | 0 |
| 0.2 × 2 | 0.4 | 0 |
| 0.4 × 2 | 0.8 | 0 |
| 0.8 × 2 | 1.6 | 1 |
| 0.6 × 2 | 1.2 | 1 |
| 0.2 × 2 | 0.4 | 0 ← pattern repeats |
0.1₁₀ = 0.000110011001100...₂ (repeating 0011). So it can only be approximated, which causes small rounding errors in digital systems.
6.6 Fractions in octal and hex
Decimal fraction → Octal (multiply by 8):
0.65625 × 8 = 5.25 → 5; 0.25 × 8 = 2.0 → 2 → 0.65625₁₀ = (0.52)₈ ✅
Decimal fraction → Hex (multiply by 16):
0.828125 × 16 = 13.25 → D; 0.25 × 16 = 4.0 → 4 → 0.828125₁₀ = (0.D4)₁₆ ✅
6.7 Grouping rule with a radix point
- Group bits outward from the point: integer part to the left (pad zeros on the left), fraction part to the right (pad zeros on the right).
Binary → Octal: 110.101₂ → 110 . 101 → (6.5)₈
Binary → Hex: 1011.11₂ → 1011 . 1100 (pad right with zeros) → (B.C)₁₆
Hex → Binary: (A.8)₁₆ → 1010 . 1000 → 1010.1₂
⚠️ Pad the fraction on the right, never on the left, or the value changes.
7. Radix and Positional Notation
7.1 Radix (base)
The radix r is the number of distinct digits in a number system. The digits run from 0 to r − 1.
| Radix | System | Largest digit |
|---|---|---|
| 2 | Binary | 1 |
| 8 | Octal | 7 |
| 10 | Decimal | 9 |
| 16 | Hexadecimal | F (15) |
Any radix ≥ 2 is possible (base 3, base 5, ...).
7.2 Positional notation
In a positional system, a digit's value = digit × radix^position. The same digit means different things in different places.
For a number with n integer digits and m fractional digits:
N = dₙ₋₁·rⁿ⁻¹ + ... + d₁·r¹ + d₀·r⁰ . d₋₁·r⁻¹ + d₋₂·r⁻² + ... + d₋ₘ·r⁻ᵐ
└──────────── integer part ─────────┘ └────── fractional part ──────┘
Or compactly: N = Σ dᵢ × rⁱ (summed over all positions, i from −m to n−1).
7.3 Position numbering
- Integer part: positions 0, 1, 2, ... counting leftwards from the point.
- Fractional part: positions −1, −2, −3, ... counting rightwards from the point.
7.4 Worked example in an unusual base
(342.1)₅ (base 5):
= 3×5² + 4×5¹ + 2×5⁰ + 1×5⁻¹ = 75 + 20 + 2 + 0.2 = 97.2₁₀
Decimal → base 5: 47
| Division | Quotient | Remainder |
|---|---|---|
| 47 ÷ 5 | 9 | 2 |
| 9 ÷ 5 | 1 | 4 |
| 1 ÷ 5 | 0 | 1 |
47₁₀ = (142)₅ ✅ (25 + 20 + 2 = 47)
7.5 Useful formulas
| Question | Formula |
|---|---|
| Different values with n digits | rⁿ |
| Largest number with n digits | rⁿ − 1 |
| Digits needed for decimal value N in base r | smallest n such that rⁿ > N |
| Bits per octal digit | 3 (since 2³ = 8) |
| Bits per hex digit | 4 (since 2⁴ = 16) |
7.6 Writing the base
Use a subscript to avoid confusion: 101₂ (five) vs 101₁₀ (one hundred one) vs 101₁₆ (257).
7.7 The general conversion rules (for any radix r)
- To decimal: multiply each digit by
rⁱand add. - From decimal (integer part): repeatedly divide by r, collect remainders.
- From decimal (fraction part): repeatedly multiply by r, collect integer parts.
8. BCD (Binary-Coded Decimal)
8.1 What is BCD?
BCD represents each decimal digit (0–9) separately using its own 4-bit binary code. Instead of converting the whole number to binary, we convert digit by digit.
This is the 8421 BCD (natural BCD), where the weights of the 4 bits are 8, 4, 2, 1.
8.2 BCD table
| Decimal digit | BCD (8421) |
|---|---|
| 0 | 0000 |
| 1 | 0001 |
| 2 | 0010 |
| 3 | 0011 |
| 4 | 0100 |
| 5 | 0101 |
| 6 | 0110 |
| 7 | 0111 |
| 8 | 1000 |
| 9 | 1001 |
8.3 Invalid (unused) codes
1010, 1011, 1100, 1101, 1110, 1111 (6 combinations) are not valid BCD. They are called forbidden / invalid / don't-care codes.
8.4 Converting
Decimal → BCD: replace each digit with its 4-bit code.
59₁₀ → 5=0101, 9=1001 → 0101 1001 (BCD)
BCD → Decimal: split into groups of 4 from the right, decode each.
1001 0011 0111 → 9, 3, 7 → 937₁₀
8.5 BCD is not the same as binary!
| Decimal | Pure binary | BCD |
|---|---|---|
| 25 | 11001 (5 bits) | 0010 0101 (8 bits) |
| 59 | 111011 | 0101 1001 |
BCD needs more bits than pure binary because 6 of the 16 four-bit combinations are wasted, so it is less storage-efficient.
8.6 Packed vs unpacked BCD
- Packed BCD: two digits per byte (e.g.
0101 1001= 59). - Unpacked BCD: one digit per byte, with the upper nibble filled with zeros (e.g.
0000 0101,0000 1001).
8.7 BCD addition (advanced)
Add the numbers as ordinary binary, digit group by digit group. After adding each 4-bit group:
If the group sum is greater than 9 (1001) OR a carry came out of the group, add 0110 (6) to that group.
Why 6? Because 6 invalid codes are skipped between 9 and 16. Adding 6 jumps over them and produces the proper carry to the next digit.
Example 1: 8 + 5
1000 (8)
+ 0101 (5)
------
1101 > 9 → invalid
+ 0110 add 6
------
1 0011 → carry 1, digit 3 → 0001 0011 = 13 ✅
Example 2: 27 + 35
0010 0111 (27)
+ 0011 0101 (35)
-----------
Low digit : 0111 + 0101 = 1100 (>9) → +0110 = 1 0010 → digit 2, carry 1
High digit: 0010 + 0011 + 1 (carry) = 0110 → digit 6
Result: 0110 0010 = 62 ✅
8.8 Advantages and disadvantages
| ✅ Advantages | ❌ Disadvantages |
|---|---|
| Easy conversion to/from decimal (digit by digit) | Needs more bits than pure binary |
| Ideal for decimal displays (calculators, digital clocks, meters) | Arithmetic is more complex (needs the +6 correction) |
| No rounding errors for decimal fractions | 6 of 16 codes are wasted |
9. 8421, 2421 and Other Weighted Codes
9.1 What is a weighted code?
In a weighted code, each bit position carries a fixed weight. The decimal value of a code word is the sum of the weights of the positions that contain a 1.
9.2 8421 code (natural BCD)
- Weights: 8, 4, 2, 1
- This is the standard BCD from Section 8. It is the same as the pure binary values 0–9.
- Example:
0111 = 4 + 2 + 1 = 7
9.3 2421 code
- Weights: 2, 4, 2, 1
- It is self-complementing (explained below).
- Note that codes for 5–9 are not the same as 8421.
9.4 5421 code
- Weights: 5, 4, 2, 1
9.5 84-2-1 code
- Weights: 8, 4, −2, −1 (two negative weights).
- Also self-complementing.
- Example:
0111 = 0 + 4 − 2 − 1 = 1
9.6 Comparison table
| Decimal | 8421 | 2421 | 5421 | 84-2-1 |
|---|---|---|---|---|
| 0 | 0000 | 0000 | 0000 | 0000 |
| 1 | 0001 | 0001 | 0001 | 0111 |
| 2 | 0010 | 0010 | 0010 | 0110 |
| 3 | 0011 | 0011 | 0011 | 0101 |
| 4 | 0100 | 0100 | 0100 | 0100 |
| 5 | 0101 | 1011 | 1000 | 1011 |
| 6 | 0110 | 1100 | 1001 | 1010 |
| 7 | 0111 | 1101 | 1010 | 1001 |
| 8 | 1000 | 1110 | 1011 | 1000 |
| 9 | 1001 | 1111 | 1100 | 1111 |
Check examples
- 2421:
1011 = 2 + 0 + 2 + 1 = 5✅ - 2421:
1101 = 2 + 4 + 0 + 1 = 7✅ - 5421:
1010 = 5 + 0 + 2 + 0 = 7✅ - 84-2-1:
1011 = 8 + 0 − 2 − 1 = 5✅
9.7 Self-complementing codes
A code is self-complementing if the 9's complement of a decimal digit is obtained simply by inverting every bit (1's complement) of its code.
Condition: the weights must add up to 9.
- 2421 → 2+4+2+1 = 9 ✅
- 84-2-1 → 8+4−2−1 = 9 ✅
- 8421 → 15 ❌ (not self-complementing)
- 5421 → 12 ❌ (not self-complementing)
Example (2421):
- Digit 2 =
0010. Invert →1101= 7. And 9 − 2 = 7 ✅ - Digit 4 =
0100. Invert →1011= 5. And 9 − 4 = 5 ✅
Example (84-2-1): Digit 1 = 0111. Invert → 1000 = 8. And 9 − 1 = 8 ✅
💡 Self-complementing codes make subtraction using 9's complement very easy in decimal arithmetic circuits.
9.8 Weighted vs non-weighted codes
| Weighted | Non-weighted |
|---|---|
| 8421, 2421, 5421, 84-2-1 | Excess-3, Gray code |
| Value = sum of weights | Bits have no fixed weights |
(Excess-3 is covered next; it is self-complementing but not weighted.)
10. Excess-3 Code
10.1 Definition
Excess-3 (XS-3) is a BCD-like code obtained by adding 3 (0011) to the 8421 BCD code of each decimal digit.
XS-3 code = BCD code + 0011
10.2 Excess-3 table
| Decimal | 8421 BCD | + 3 | Excess-3 |
|---|---|---|---|
| 0 | 0000 | +0011 | 0011 |
| 1 | 0001 | +0011 | 0100 |
| 2 | 0010 | +0011 | 0101 |
| 3 | 0011 | +0011 | 0110 |
| 4 | 0100 | +0011 | 0111 |
| 5 | 0101 | +0011 | 1000 |
| 6 | 0110 | +0011 | 1001 |
| 7 | 0111 | +0011 | 1010 |
| 8 | 1000 | +0011 | 1011 |
| 9 | 1001 | +0011 | 1100 |
Unused (invalid) codes: 0000, 0001, 0010, 1101, 1110, 1111.
10.3 Key properties
- It is a non-weighted code.
- It is self-complementing: inverting all bits gives the 9's complement.
- Digit 2 =
0101. Invert →1010= 7 ✅ (9 − 2 = 7) - Digit 0 =
0011. Invert →1100= 9 ✅
- Digit 2 =
- No all-zero code (0000 is not used), so a broken wire or lost signal showing
0000can be detected as an error. - Excess-3 digits 0 and 9 are
0011and1100, which are bit-wise complements.
10.4 Conversions
Decimal → XS-3: convert each digit to BCD, then add 0011.
47 → 4=0100+0011=0111, 7=0111+0011=1010 → 0111 1010
XS-3 → Decimal: subtract 0011 from each group, then decode.
1000 1100 → 1000−0011=0101=5, 1100−0011=1001=9 → 59
10.5 Excess-3 addition (advanced)
Add the two XS-3 numbers digit group by group using binary addition, then correct:
| Condition after adding a group | Correction |
|---|---|
| A carry is generated | Add 3 (0011) to that group |
| No carry is generated | Subtract 3 (0011) from that group (i.e. add 1101) |
Why? Each XS-3 digit already carries an excess of 3, so adding two of them gives an excess of 6, but the result should carry an excess of only 3.
- No carry: the group is 3 too high, so subtract 3.
- Carry out: the carry takes away 16 while the digit should only have lost 10, so the group is 6 too low. Adding 6 would fix that, but we also need the excess of 3 back, so we add 3 in total (6 − 3 = 3).
Example: 4 + 3
0111 (4 in XS-3)
+ 0110 (3 in XS-3)
------
1101 no carry → subtract 0011
- 0011
------
1010 = 7 in XS-3 ✅
11. Gray Code and Binary-to-Gray Conversion
11.1 What is Gray code?
Gray code (also called reflected binary code) is a non-weighted code in which only one bit changes between any two consecutive numbers. This is called the unit-distance property.
11.2 Why is it useful?
In normal binary, several bits can change at once (e.g. 0111 → 1000 changes 4 bits). If the bits do not switch at exactly the same instant, a wrong intermediate value may appear. Gray code avoids this.
Typical uses: rotary/shaft position encoders, analog-to-digital converters, and error reduction in digital communication.
11.3 Gray code table (4-bit)
| Decimal | Binary | Gray |
|---|---|---|
| 0 | 0000 | 0000 |
| 1 | 0001 | 0001 |
| 2 | 0010 | 0011 |
| 3 | 0011 | 0010 |
| 4 | 0100 | 0110 |
| 5 | 0101 | 0111 |
| 6 | 0110 | 0101 |
| 7 | 0111 | 0100 |
| 8 | 1000 | 1100 |
| 9 | 1001 | 1101 |
| 10 | 1010 | 1111 |
| 11 | 1011 | 1110 |
| 12 | 1100 | 1010 |
| 13 | 1101 | 1011 |
| 14 | 1110 | 1001 |
| 15 | 1111 | 1000 |
Look down the Gray column: every step changes exactly one bit. Even 15 → 0 (1000 → 0000) changes only one bit, so the code is cyclic.
11.4 Binary → Gray conversion
Rules
- The MSB of Gray = MSB of binary (copy it).
- Each next Gray bit = XOR of the current binary bit and the previous (left) binary bit.
G₃ = B₃
G₂ = B₃ ⊕ B₂
G₁ = B₂ ⊕ B₁
G₀ = B₁ ⊕ B₀
XOR reminder: 0⊕0=0, 0⊕1=1, 1⊕0=1, 1⊕1=0 (same → 0, different → 1).
Example: 1011₂ → Gray
Binary : 1 0 1 1
│ ↓ ↓ ↓
Gray : 1 1⊕0 0⊕1 1⊕1
=1 =1 =1 =0
1011₂ → 1110 (Gray) ✅ (matches the table, decimal 11)
11.5 Gray → Binary conversion
Rules
- The MSB of binary = MSB of Gray (copy it).
- Each next binary bit = XOR of the previous (left) binary bit and the current Gray bit.
B₃ = G₃
B₂ = B₃ ⊕ G₂
B₁ = B₂ ⊕ G₁
B₀ = B₁ ⊕ G₀
Example: Gray 1110 → Binary
B₃ = 1
B₂ = 1 ⊕ 1 = 0
B₁ = 0 ⊕ 1 = 1
B₀ = 1 ⊕ 0 = 1
1110 (Gray) → 1011₂ ✅
11.6 Constructing Gray code by reflection
To build an (n+1)-bit Gray code from an n-bit code:
- Write the n-bit Gray sequence.
- Reflect (mirror) it below itself.
- Add a 0 in front of the upper half and a 1 in front of the lower half.
1-bit 2-bit 3-bit
0 00 000
1 01 001
────── 011
11 010
10 ────────
110
111
101
100
11.7 Quick check
- Binary and Gray are the same for 0 and 1 (
0 → 0,1 → 1). - The Gray code of any number can be found by
G = B ⊕ (B shifted right by 1).
12. Alphanumeric Codes: ASCII and Unicode
Computers store only bits, so letters, digits and symbols must also be given binary codes. Codes that represent alphabets, numbers and special characters are called alphanumeric codes.
12.1 ASCII
ASCII = American Standard Code for Information Interchange.
- Uses 7 bits → 128 characters (codes 0 to 127).
- Usually stored in 8 bits (1 byte), where the extra bit is
0or used as a parity bit for error detection. - Extended ASCII uses all 8 bits → 256 characters (codes 0–255), adding accented letters and symbols. (Different versions of extended ASCII exist.)
ASCII layout
| Code range (decimal) | What it contains |
|---|---|
| 0 – 31 | Control characters (non-printable): e.g. NUL(0), BEL(7), BS(8), TAB(9), LF(10), CR(13), ESC(27) |
| 32 | Space |
| 33 – 47 | Punctuation and symbols (! " # $ % & ' ( ) * + , - . /) |
| 48 – 57 | Digits 0–9 |
| 58 – 64 | More symbols (: ; < = > ? @) |
| 65 – 90 | Uppercase A–Z |
| 91 – 96 | Symbols ([ \ ] ^ _ `` ``) |
| 97 – 122 | Lowercase a–z |
| 123 – 126 | Symbols ({ | } ~) |
| 127 | DEL (delete) |
Selected ASCII codes
| Character | Decimal | Hex | Binary (7-bit) |
|---|---|---|---|
0 | 48 | 30 | 0110000 |
9 | 57 | 39 | 0111001 |
A | 65 | 41 | 1000001 |
Z | 90 | 5A | 1011010 |
a | 97 | 61 | 1100001 |
z | 122 | 7A | 1111010 |
| Space | 32 | 20 | 0100000 |
Handy patterns
- Digit → number: ASCII of digit
'7'is 55; subtract 48 (or take the lower nibble) to get 7.- ASCII digits in hex are
30–39, so the lower nibble equals the digit.
- ASCII digits in hex are
- Uppercase → lowercase: add 32 (or set bit 5).
'A'(65) + 32 ='a'(97). - Letters are in alphabetical order, so sorting by code sorts alphabetically.
Example: the word "Hi"
H = 72 = 01001000, i = 105 = 01101001
Parity bit (error detection)
An 8th bit can be added so the total number of 1s is even (even parity) or odd (odd parity).
'A'=1000001has two 1s → even parity bit =0→01000001.'C'=1000011has three 1s → even parity bit =1→11000011.
Limitation of ASCII
It only covers English letters and basic symbols. It cannot represent other languages such as Hindi, Chinese or Arabic, nor emojis.
12.2 Unicode
Unicode is a universal standard that assigns a unique number (code point) to every character in every writing system, plus symbols and emojis.
- Code points are written as U+XXXX in hex (e.g.
U+0041=A). - Range: U+0000 to U+10FFFF (over 1.1 million possible code points; well over 140,000 are assigned).
- The first 128 code points are identical to ASCII, so ASCII text is valid Unicode (backward compatibility).
- Organised into planes. The most common characters live in the Basic Multilingual Plane (BMP), U+0000 to U+FFFF.
Examples
| Character | Code point | Meaning |
|---|---|---|
| A | U+0041 | Latin capital A (same as ASCII) |
| अ | U+0905 | Devanagari letter A |
| € | U+20AC | Euro sign |
| 😀 | U+1F600 | Grinning face emoji |
12.3 Unicode encodings (how code points become bytes)
A code point is just a number. An encoding decides how it is stored in bytes.
| Encoding | Size per character | Notes |
|---|---|---|
| UTF-8 | 1 to 4 bytes (variable) | Most popular on the web; ASCII-compatible (1 byte for ASCII) |
| UTF-16 | 2 or 4 bytes | Used internally by some systems and languages |
| UTF-32 | Always 4 bytes | Simple but uses more memory |
UTF-8 structure
| Code point range | Bytes | Byte pattern |
|---|---|---|
| U+0000 – U+007F | 1 | 0xxxxxxx |
| U+0080 – U+07FF | 2 | 110xxxxx 10xxxxxx |
| U+0800 – U+FFFF | 3 | 1110xxxx 10xxxxxx 10xxxxxx |
| U+10000 – U+10FFFF | 4 | 11110xxx 10xxxxxx 10xxxxxx 10xxxxxx |
The x positions are filled with the bits of the code point.
UTF-8 examples
| Character | Code point | UTF-8 bytes (hex) | Bytes |
|---|---|---|---|
| A | U+0041 | 41 | 1 |
| अ | U+0905 | E0 A4 85 | 3 |
| € | U+20AC | E2 82 AC | 3 |
| 😀 | U+1F600 | F0 9F 98 80 | 4 |
Worked example: € (U+20AC) → 3-byte pattern:
20AC = 0010 0000 1010 1100 → 1110 0010 | 10 000010 | 10 101100 → E2 82 AC ✅
12.4 ASCII vs Unicode
| Feature | ASCII | Unicode |
|---|---|---|
| Bits | 7 (stored in 8) | Up to 21 bits per code point |
| Characters | 128 | Over 1.1 million code points possible |
| Languages | English only | All major world scripts and emojis |
| Encodings | One | UTF-8, UTF-16, UTF-32 |
| Compatibility | Base standard | First 128 characters = ASCII |
📝 Quick Revision Cheat Sheet
| Topic | Remember this |
|---|---|
| Decimal / Binary / Octal / Hex | Base 10 / 2 / 8 / 16 |
| Octal ↔ Binary | 1 octal digit = 3 bits |
| Hex ↔ Binary | 1 hex digit = 4 bits |
| Any base → Decimal | Digit × radix^position, then add |
| Decimal → Any base (integer) | Divide repeatedly, read remainders upward |
| Decimal → Any base (fraction) | Multiply repeatedly, read integer parts downward |
| Grouping with a point | Integer part: pad left; fractional part: pad right |
| n-digit range in base r | 0 to rⁿ − 1 |
| BCD | Each decimal digit → 4 bits (8421); 1010–1111 invalid |
| BCD addition fix | Add 0110 if group > 9 or carry out |
| Self-complementing code condition | Weights add to 9 (2421, 84-2-1) |
| Excess-3 | BCD + 0011; self-complementing, non-weighted |
| XS-3 addition fix | Carry → add 3; no carry → subtract 3 |
| Gray code | One bit changes between consecutive numbers |
| Binary → Gray | G_MSB = B_MSB; Gᵢ = Bᵢ ⊕ Bᵢ₊₁ |
| Gray → Binary | B_MSB = G_MSB; Bᵢ = Bᵢ₊₁ ⊕ Gᵢ |
| ASCII | 7-bit, 128 characters; 'A' = 65, 'a' = 97, '0' = 48 |
| Upper → lower in ASCII | Add 32 |
| Unicode | Universal code points (U+XXXX); UTF-8 is 1–4 bytes |
🧠 Practice Questions
- Convert (237)₁₀ to binary, octal and hexadecimal.
- Convert (1011011)₂ to decimal, octal and hex.
- Convert (3B5)₁₆ to binary and octal.
- Convert (0.8125)₁₀ to binary.
- Convert (110.101)₂ to decimal and octal.
- Convert (25.375)₁₀ to binary.
- Write the number of digits needed to represent decimal 1000 in binary.
- Express (86)₁₀ in BCD and in Excess-3.
- Add BCD 0110 and BCD 0111 (6 + 7) and give the BCD result.
- Why is 2421 self-complementing but 8421 is not?
- Convert binary 1101 to Gray code and Gray 1001 to binary.
- Write the ASCII code (decimal and binary) of
'B'and'b'. - Explain how UTF-8 stays compatible with ASCII.
Click for answers
- 237 = 11101101₂ = (355)₈ = (ED)₁₆
- 1011011₂ = 64 + 16 + 8 + 2 + 1 = 91₁₀ = (133)₈ = (5B)₁₆
- 3B5₁₆ =
0011 1011 0101= 1110110101₂ → groups of 3:001 110 110 101= (1665)₈ - 0.8125 × 2 = 1.625 (1); 0.625 × 2 = 1.25 (1); 0.25 × 2 = 0.5 (0); 0.5 × 2 = 1.0 (1) → 0.1101₂
- 110.101₂ = 4 + 2 + 0.5 + 0.125 = 6.625₁₀ = (6.5)₈
- 25 = 11001; 0.375 → 0.011 → 11001.011₂
- 2¹⁰ = 1024 > 1000 → 10 bits
- 86 → BCD: 1000 0110; Excess-3: 1011 1001 → 1011 1001 (8+3 = 11 = 1011, 6+3 = 9 = 1001)
- 0110 + 0111 = 1101 (>9) → +0110 = 1 0011 → 0001 0011 = 13
- The weights of 2421 sum to 9 (2+4+2+1), so inverting the bits gives the 9's complement. 8421 weights sum to 15, so it does not.
- 1101 → G = 1, 1⊕1=0, 1⊕0=1, 0⊕1=1 → 1011. Gray 1001 → B = 1, 1⊕0=1, 1⊕0=1, 1⊕1=0 → 1110
- 'B' = 66 = 1000010; 'b' = 98 = 1100010
- The first 128 Unicode code points equal ASCII, and UTF-8 stores them in a single byte of the form
0xxxxxxx, identical to ASCII bytes.
##Binary Arithmetic and Signed Numbers#
Friendly, structured notes for Unit 3: Binary Arithmetic and Signed Numbers. Read in order the first time. Every rule comes with a worked example, and a cheat sheet and practice questions are at the end.
📑 Table of Contents
- Binary Addition and Subtraction
- Binary Multiplication and Division
- 1's Complement and 2's Complement
- Signed Magnitude Representation
- Signed and Unsigned Number Representation
- Range of n-bit Numbers
- Overflow and Underflow
- Sign Extension
- BCD Arithmetic
- BCD Addition and Correction
- Fixed-Point Number Representation
- Introduction to Floating-Point Representation
- Quick Revision Cheat Sheet
🧭 Big Picture
Digital systems only have bits, so we need answers to three questions:
- How do we calculate with bits? → Sections 1, 2, 9, 10
- How do we show negative numbers with only 0s and 1s? → Sections 3, 4, 5, 6, 8
- How do we show fractions and very large or small numbers? → Sections 11, 12
And one question about limits: what happens when a result does not fit? → Section 7
Number representations
│
┌───────────────────┼────────────────────┐
Unsigned Signed Real numbers
(0 … 2ⁿ−1) ┌────────┼─────────┐ ┌──────┴───────┐
Sign- 1's 2's Fixed- Floating-
magnitude comp. comp. point point
1. Binary Addition and Subtraction
1.1 Binary addition rules
| A | B | Sum | Carry |
|---|---|---|---|
| 0 | 0 | 0 | 0 |
| 0 | 1 | 1 | 0 |
| 1 | 0 | 1 | 0 |
| 1 | 1 | 0 | 1 |
With an incoming carry, 1 + 1 + 1 = 1 with a carry of 1 (because 1+1+1 = 3 = 11₂).
Memory aid: 1 + 1 = 10₂ → write 0, carry 1.
1.2 Method
Add column by column from the right (LSB) to the left (MSB), passing the carry to the next column, exactly like decimal addition.
1.3 Example: 1011 + 0110 (11 + 6 = 17)
carry: 1 1 1 .
1 0 1 1 (11)
+ 0 1 1 0 ( 6)
---------
1 0 0 0 1 (17) ✅
Column by column: 1+0=1 · 1+1=0 c1 · 0+1+1=0 c1 · 1+0+1=0 c1 · final carry 1.
Note the result needs one more bit (5 bits) than the operands (4 bits). That extra bit is the carry-out, which becomes important in Section 7.
1.4 Binary subtraction rules
| A | B | Difference | Borrow |
|---|---|---|---|
| 0 | 0 | 0 | 0 |
| 0 | 1 | 1 | 1 |
| 1 | 0 | 1 | 0 |
| 1 | 1 | 0 | 0 |
When you do 0 − 1, you borrow 1 from the next higher column. That column drops by 1, and the current column becomes 10₂ − 1 = 1.
1.5 Example: 1101 − 0110 (13 − 6 = 7)
borrow: . 1 1 .
1 1 0 1 (13)
− 0 1 1 0 ( 6)
---------
0 1 1 1 ( 7) ✅
1.6 Example: 1000 − 0011 (8 − 3 = 5)
1 0 0 0
− 0 0 1 1
---------
0 1 0 1 (5) ✅
1.7 A better way to subtract
Borrowing is awkward in hardware. Digital systems usually turn subtraction into addition using complements: A − B = A + (−B). This is why complements (Section 3) are so important. The same adder circuit can then do both jobs.
2. Binary Multiplication and Division
2.1 Multiplication rules (one bit)
| A | B | A × B |
|---|---|---|
| 0 | 0 | 0 |
| 0 | 1 | 0 |
| 1 | 0 | 0 |
| 1 | 1 | 1 |
It is just the AND operation. This makes binary multiplication much simpler than decimal.
2.2 Method: shift and add
- For each bit of the multiplier (right to left):
- If the bit is 1 → write a copy of the multiplicand.
- If the bit is 0 → write all zeros.
- Shift each partial product one place left for each step.
- Add all partial products.
2.3 Example: 1011 × 101 (11 × 5 = 55)
1 0 1 1 (multiplicand = 11)
× 1 0 1 (multiplier = 5)
---------
1 0 1 1 ← × 1 (bit 0)
0 0 0 0 . ← × 0 (bit 1), shifted 1
1 0 1 1 . . ← × 1 (bit 2), shifted 2
-------------
1 1 0 1 1 1 = 55 ✅
2.4 Result size
Multiplying an m-bit number by an n-bit number gives a product of up to m + n bits.
2.5 Shortcut: multiplying by powers of 2
Shifting left by k positions multiplies by 2ᵏ.
0011₂ (3) shifted left 2 places → 1100₂ (12) ✅ (3 × 4)
2.6 Binary division (long division)
It works like decimal long division, but each quotient bit is only 0 or 1: "does the divisor fit?"
- Take enough leading bits of the dividend to compare with the divisor.
- If the divisor fits → quotient bit = 1, subtract the divisor.
- If it does not fit → quotient bit = 0.
- Bring down the next bit and repeat.
2.7 Example: 110101 ÷ 101 (53 ÷ 5 = 10 remainder 3)
1 0 1 0 ← quotient (1010₂ = 10)
┌───────────
101 ) 1 1 0 1 0 1
− 1 0 1
-------
0 0 1 1 ← bring down 1: 011 (3) < 101 → quotient bit 0
0 1 1 0 ← bring down 0: 0110 (6) ≥ 101 → quotient bit 1
− 1 0 1
---------
0 0 1 1 ← bring down 1: 011 (3) < 101 → quotient bit 0
remainder = 011₂ = 3
Quotient 1010₂ = 10, remainder 011₂ = 3 → check: 5 × 10 + 3 = 53 ✅
2.8 Shortcut: dividing by powers of 2
Shifting right by k positions divides by 2ᵏ (for unsigned numbers; the bits shifted out form the remainder).
1100₂ (12) shifted right 2 places → 0011₂ (3) ✅
3. 1's Complement and 2's Complement
Complements are the standard way to represent negative numbers and to subtract using addition.
3.1 1's complement
Flip every bit (0 → 1, 1 → 0).
| Number | 1's complement |
|---|---|
| 0110 | 1001 |
| 1101 | 0010 |
| 00000000 | 11111111 |
3.2 2's complement
2's complement = 1's complement + 1
Example: 2's complement of 0110 (6)
0110 original
1001 1's complement (invert)
+ 1 add 1
----
1010 2's complement → represents −6
3.3 Shortcut for the 2's complement
Starting from the right (LSB), copy bits up to and including the first 1, then invert all the remaining bits on the left.
01100100 → copy 100 from the right, invert the rest 01100 → 10011 → 10011100
Check by the long method: invert 01100100 → 10011011, add 1 → 10011100 ✅
3.4 Handy facts
- The 2's complement of the 2's complement gives back the original number.
- 2's complement of 0 is 0 (
0000 → 1111 + 1 = 10000, and the carry out of 4 bits is dropped). - The 2's complement of
N(in n bits) equals2ⁿ − N. - The 1's complement of
N(in n bits) equals(2ⁿ − 1) − N.
3.5 Subtraction using 2's complement
Rule: A − B = A + (2's complement of B)
- If a carry-out is generated → the result is positive; discard the carry. The remaining bits are the answer.
- If no carry-out → the result is negative; the answer is the 2's complement of the sum, with a negative sign.
Example 1: 1101 − 0110 (13 − 6)
1101
+ 1010 (2's complement of 0110)
------
1 0111 carry = 1 → positive, discard carry
0111 = 7 ✅
Example 2: 0110 − 1101 (6 − 13)
0110
+ 0011 (2's complement of 1101)
------
1001 no carry → negative
Magnitude = 2's complement of 1001 = 0111 = 7 → −7 ✅
3.6 Subtraction using 1's complement
Rule: A − B = A + (1's complement of B)
- If a carry-out is generated → add it back to the LSB (end-around carry); the result is positive.
- If no carry-out → the result is negative; the answer is the 1's complement of the sum, with a negative sign.
Example 1: 1101 − 0110
1101
+ 1001 (1's complement of 0110)
------
1 0110 carry = 1
+ 1 end-around carry
------
0111 = 7 ✅
Example 2: 0110 − 1101
0110
+ 0010 (1's complement of 1101)
------
1000 no carry → negative
Magnitude = 1's complement of 1000 = 0111 → −7 ✅
3.7 1's vs 2's complement
| Feature | 1's complement | 2's complement |
|---|---|---|
| How to get it | Invert bits | Invert bits, then add 1 |
| Zero | Two zeros (+0 and −0) | One zero |
| Subtraction carry | End-around carry needed | Carry simply discarded |
| Hardware | Slightly more complex | Simpler, most widely used |
4. Signed Magnitude Representation
4.1 Idea
The most natural way to show a sign, like writing "+" or "−" in front of a number.
- The MSB is the sign bit:
0= positive,1= negative. - The remaining n−1 bits hold the magnitude (absolute value) in ordinary binary.
Sign Magnitude
┌───┐ ┌───────────┐
│ S │ │ b₆ ... b₀ │ (example: 8-bit number)
└───┘ └───────────┘
4.2 Examples (8-bit)
| Decimal | Signed magnitude |
|---|---|
| +25 | 0 0011001 = 00011001 |
| −25 | 1 0011001 = 10011001 |
| +0 | 0 0000000 = 00000000 |
| −0 | 1 0000000 = 10000000 |
Only the sign bit differs between +25 and −25.
4.3 Range
For n bits: −(2ⁿ⁻¹ − 1) to +(2ⁿ⁻¹ − 1). For 8 bits: −127 to +127.
4.4 Arithmetic in signed magnitude
- Same signs: add the magnitudes; keep the common sign.
- Different signs: compare magnitudes, subtract the smaller from the larger, and use the sign of the larger magnitude.
Example: (+5) + (−3): signs differ; 5 > 3 → 5 − 3 = 2, sign of larger (+) → +2 ✅
4.5 Pros and cons
| ✅ Advantages | ❌ Disadvantages |
|---|---|
| Very easy for humans to read | Two representations of zero (+0 and −0) |
| Easy sign change (flip one bit) | Needs separate logic to compare magnitudes and choose the operation |
| Symmetric range | Adder hardware is more complex than for 2's complement |
5. Signed and Unsigned Number Representation
5.1 Unsigned numbers
- All n bits represent the magnitude. No negative numbers.
- Range: 0 to 2ⁿ − 1.
- Example:
1011₂= 8 + 2 + 1 = 11.
5.2 Signed numbers
- Can represent positive, negative and zero.
- One bit (the MSB) acts as, or contributes to, the sign.
- Three common schemes: signed magnitude, 1's complement, 2's complement.
5.3 The same bits mean different things
The pattern 1011 is:
| Interpretation | Value |
|---|---|
| Unsigned | 11 |
| Signed magnitude | −3 |
| 1's complement | −4 |
| 2's complement | −5 |
⚠️ The hardware does not "know" the type. The programmer or designer decides how to interpret the bits.
5.4 Comparison table (4-bit numbers)
| Decimal | Signed magnitude | 1's complement | 2's complement |
|---|---|---|---|
| +7 | 0111 | 0111 | 0111 |
| +6 | 0110 | 0110 | 0110 |
| +5 | 0101 | 0101 | 0101 |
| +4 | 0100 | 0100 | 0100 |
| +3 | 0011 | 0011 | 0011 |
| +2 | 0010 | 0010 | 0010 |
| +1 | 0001 | 0001 | 0001 |
| +0 | 0000 | 0000 | 0000 |
| −0 | 1000 | 1111 | — (does not exist) |
| −1 | 1001 | 1110 | 1111 |
| −2 | 1010 | 1101 | 1110 |
| −3 | 1011 | 1100 | 1101 |
| −4 | 1100 | 1011 | 1100 |
| −5 | 1101 | 1010 | 1011 |
| −6 | 1110 | 1001 | 1010 |
| −7 | 1111 | 1000 | 1001 |
| −8 | — | — | 1000 |
Positive numbers look identical in all three schemes. Only negative numbers differ.
5.5 Reading a 2's complement number
Method 1: weighted sum. The MSB has a negative weight of −2ⁿ⁻¹; all other bits have their usual positive weights.
1011 (4-bit) = −8 + 0 + 2 + 1 = −5 ✅
Method 2: complement. If the MSB is 1, the number is negative. Take the 2's complement to get the magnitude.
1011 → invert 0100 → +1 → 0101 = 5 → −5 ✅
5.6 Writing a negative number in 2's complement
- Write the positive value in binary (with enough bits).
- Take the 2's complement.
−18 in 8-bit: +18 = 00010010 → invert 11101101 → +1 → 11101110
Check: −128 + 64 + 32 + 8 + 4 + 2 = −18 ✅
5.7 Why 2's complement wins
- One zero.
- Addition and subtraction use the same adder with no special sign handling.
- Slightly larger negative range (one extra number).
That is why almost all modern computers use 2's complement for signed integers.
6. Range of n-bit Numbers
6.1 Formulas
| Representation | Smallest | Largest | Distinct values |
|---|---|---|---|
| Unsigned | 0 | 2ⁿ − 1 | 2ⁿ |
| Signed magnitude | −(2ⁿ⁻¹ − 1) | +(2ⁿ⁻¹ − 1) | 2ⁿ − 1 (two zeros) |
| 1's complement | −(2ⁿ⁻¹ − 1) | +(2ⁿ⁻¹ − 1) | 2ⁿ − 1 (two zeros) |
| 2's complement | −2ⁿ⁻¹ | +(2ⁿ⁻¹ − 1) | 2ⁿ |
6.2 Common sizes
| n | Unsigned | Signed magnitude / 1's complement | 2's complement |
|---|---|---|---|
| 4 | 0 to 15 | −7 to +7 | −8 to +7 |
| 8 | 0 to 255 | −127 to +127 | −128 to +127 |
| 16 | 0 to 65,535 | −32,767 to +32,767 | −32,768 to +32,767 |
| 32 | 0 to 4,294,967,295 | ±2,147,483,647 | −2,147,483,648 to +2,147,483,647 |
6.3 Why is 2's complement asymmetric?
There is only one zero, so one extra bit pattern (1000...0) is free and is used for −2ⁿ⁻¹. This number has no positive counterpart. Negating it gives itself (e.g. 4-bit: −8 → 1000 → invert 0111 → +1 → 1000), a classic exception to watch for.
6.4 How many bits do I need?
- Unsigned value N: smallest n with
2ⁿ > N. (For 1000 → n = 10.) - 2's complement range up to ±N: need an extra bit for the sign. (To hold −100 to +100: 7 bits give −64..63, which is too small; 8 bits give −128..127 ✅)
7. Overflow and Underflow
7.1 What is overflow?
A fixed number of bits can only hold values in a certain range (Section 6). Overflow occurs when a result is too large (or too negative) to fit in the available bits. The stored result is then wrong.
7.2 Unsigned overflow
- Addition: overflow if there is a carry-out of the MSB.
- Subtraction: if there is a borrow out (i.e. A < B), the result would be negative, so it cannot be represented. This is sometimes called underflow.
Example (4-bit): 1001 + 1000 (9 + 8 = 17)
1001
+ 1000
------
1 0001 carry-out = 1 → overflow; stored result 0001 = 1 (wrong)
Example (unsigned underflow, 4-bit): 0011 − 0101 (3 − 5)
0011
+ 1011 (2's complement of 0101)
------
1110 no carry → borrow occurred → negative → underflow; 1110 = 14 as unsigned (wrong)
7.3 Signed (2's complement) overflow
It can happen only when adding numbers of the same sign.
| Operation | Overflow condition |
|---|---|
| Positive + Positive | Result looks negative (MSB = 1) |
| Negative + Negative | Result looks positive (MSB = 0) |
| Positive + Negative | Never overflows (result always lies between the operands) |
Detection rule (hardware):
Overflow = (carry INTO the MSB) XOR (carry OUT of the MSB)
If the two carries differ, overflow occurred.
Example 1: 0101 + 0100 (+5 + +4 = 9, but 4-bit max is +7)
0101
+ 0100
------
1001 carry into MSB = 1, carry out = 0 → XOR = 1 → OVERFLOW
1001 reads as −7 (wrong)
Example 2: 1011 + 1010 (−5 + −6 = −11, but 4-bit min is −8)
1011
+ 1010
------
1 0101 carry into MSB = 0, carry out = 1 → XOR = 1 → OVERFLOW
0101 reads as +5 (wrong)
Example 3: 0101 + 1110 (+5 + −2 = +3)
0101
+ 1110
------
1 0011 carry into MSB = 1, carry out = 1 → XOR = 0 → no overflow
0011 = +3 ✅ (the carry-out is simply discarded)
⚠️ For signed numbers, a carry-out does not mean overflow. For unsigned numbers, a carry-out does. Always check which kind of number you are using.
7.4 Underflow
The word has two common uses:
- Integer (negative overflow): the result is more negative than the smallest representable number. Example: 4-bit 2's complement
−8 + −1 = −9cannot be shown. Also used for an unsigned subtraction giving a negative answer (see 7.2). - Floating-point underflow: the result is too close to zero (smaller in magnitude than the smallest representable nonzero number) and gets rounded to zero or a special tiny value. (Introduced in Section 12.)
7.5 Overflow vs carry vs borrow
| Term | Meaning |
|---|---|
| Carry | A 1 passed to the next column, or out of the MSB |
| Borrow | Taking 1 from the next column during subtraction |
| Overflow | The result does not fit in the allotted bits |
7.6 How to avoid overflow
Use more bits (a wider word), check ranges before calculating, or use sign extension (next section) to widen operands before adding.
8. Sign Extension
8.1 What is it?
Sign extension increases the number of bits of a signed number without changing its value, for example turning a 4-bit number into an 8-bit number so it can be used with other 8-bit values.
8.2 Rule for 2's complement (and 1's complement)
Copy the sign bit (MSB) into all the new, higher-order bits.
| 4-bit | Value | 8-bit (sign-extended) | Value |
|---|---|---|---|
0101 | +5 | 0000 0101 | +5 ✅ |
1011 | −5 | 1111 1011 | −5 ✅ |
1000 | −8 | 1111 1000 | −8 ✅ |
Proof for 1011 → 11111011: −128 + 64 + 32 + 16 + 8 + 0 + 2 + 1 = −5 ✅
Why it works: Take an n-bit negative number whose MSB (weight −2ⁿ⁻¹) is 1. After adding one new MSB equal to 1, the new MSB has weight −2ⁿ and the old MSB now has weight +2ⁿ⁻¹. Their combined contribution is −2ⁿ + 2ⁿ⁻¹ = −2ⁿ⁻¹, exactly what the old MSB contributed alone. So the value is unchanged, and repeating this adds as many extra 1s as you like. For a positive number the sign bit is 0, and extra 0s obviously change nothing.
8.3 Rule for signed magnitude
The sign bit is a separate field, so move it to the new MSB and fill the gap with zeros (the magnitude is unchanged).
1011 (−3) → 1000 0011 (−3) ✅
8.4 Rule for unsigned numbers
Just add zeros on the left. This is zero extension.
1011 (11) → 0000 1011 (11) ✅
8.5 Summary
| Number type | Extension method |
|---|---|
| Unsigned | Pad with 0s on the left |
| 2's complement | Pad with copies of the MSB |
| 1's complement | Pad with copies of the MSB |
| Signed magnitude | Move the sign bit to the new MSB, pad with 0s in between |
8.6 Reverse operation: truncation
Removing high-order bits is only safe if the removed bits are all copies of the new sign bit; otherwise the value changes (overflow).
9. BCD Arithmetic
9.1 Recap
BCD (Binary-Coded Decimal) stores each decimal digit in its own 4-bit group using the 8421 weights.
47₁₀ → 0100 0111 (BCD) versus 101111₂ (pure binary)
Only the codes 0000 to 1001 (0–9) are valid. The codes 1010 to 1111 (10–15) are invalid.
9.2 Why does BCD arithmetic need special rules?
A 4-bit binary adder counts from 0 to 15, but a BCD digit must stop at 9. The six invalid codes (10–15) cause two problems:
- A digit sum from 10 to 15 gives an invalid BCD code.
- A digit sum of 16 or more gives a carry, but the digit left behind is 6 too small compared with the decimal answer, because 6 codes were skipped.
The cure is the +6 (0110) correction (Section 10).
9.3 BCD subtraction (overview)
BCD subtraction can be done with 10's complement in decimal terms, using BCD adders.
- 9's complement of a decimal digit
d=9 − d. - 10's complement of a number = 9's complement + 1 (added at the LSD).
Rule: A − B = A + (10's complement of B)
- If a carry-out from the most significant digit appears → result is positive; discard the carry.
- If no carry → result is negative; take the 10's complement of the sum for the magnitude.
Example: 74 − 38 = 36
| Step | Work |
|---|---|
| 9's complement of 38 | 99 − 38 = 61 |
| 10's complement | 61 + 1 = 62 |
| Add | 74 + 62 = 136 → carry 1 (discard) → 36 ✅ |
In BCD:
B = 0011 1000 (38)
9's complement → 0110 0001 (61)
+ 1 → 0110 0010 (62) (10's complement)
0111 0100 (74)
+ 0110 0010 (62)
-----------
Low digit : 0100 + 0010 = 0110 (6) valid, no correction
High digit: 0111 + 0110 = 1101 (13) invalid → +0110 = 1 0011 → digit 3, carry 1 (discard)
Result : 0011 0110 = 36 ✅
9.4 BCD vs binary arithmetic
| Feature | Pure binary | BCD |
|---|---|---|
| Representation | Whole number as one binary value | Digit by digit |
| Adder correction | None | +0110 when needed |
| Storage efficiency | Better | Wastes 6 of 16 codes per digit |
| Decimal exactness | Fractions like 0.1 can be inexact | Decimal digits stored exactly |
| Typical use | General computing | Calculators, digital meters, financial/decimal displays |
10. BCD Addition and Correction
10.1 The rule
Add two BCD digits (plus any carry-in) with a normal 4-bit binary adder. If the result is greater than 9 (1001), OR a carry-out was produced, add
0110(6) to that group. Any carry produced goes to the next higher digit.
10.2 Why +6?
A decimal digit wraps after 9, but a 4-bit group wraps after 15. The difference is 16 − 10 = 6. Adding 6 makes the group "skip" the six invalid codes and wrap correctly at 10, producing the proper carry.
10.3 Cases
| Binary sum of the digits (decimal) | 4-bit result | Carry-out? | Correction? | Corrected BCD |
|---|---|---|---|---|
| 0 – 9 | 0000 – 1001 | No | No | unchanged |
| 10 – 15 | 1010 – 1111 | No | Yes, +0110 | 0001 0000 – 0001 0101 |
| 16 – 19 | 0000 – 0011 | Yes | Yes, +0110 | 0001 0110 – 0001 1001 |
(The largest digit sum is 9 + 9 + 1 carry = 19.)
10.4 Example 1: No correction. 4 + 3
0100 (4)
+ 0011 (3)
------
0111 = 7, valid ✅
10.5 Example 2: Invalid code. 8 + 5
1000 (8)
+ 0101 (5)
------
1101 = 13 > 9, invalid
+ 0110 correction
------
1 0011 → digit 3, carry 1 → 0001 0011 = 13 ✅
10.6 Example 3: Carry out. 9 + 8
1001 (9)
+ 1000 (8)
------
1 0001 carry-out = 1 → correction needed
0001
+ 0110
------
0111 → digit 7, carry 1 stays → 0001 0111 = 17 ✅
10.7 Example 4: Two digits. 27 + 35 = 62
0010 0111 (27)
+ 0011 0101 (35)
-----------
Low digit : 0111 + 0101 = 1100 (12) > 9 → +0110 = 1 0010 → digit 2, carry 1
High digit: 0010 + 0011 + 1 = 0110 (6) valid
Result : 0110 0010 = 62 ✅
10.8 Example 5: Three digits with chain corrections. 586 + 497 = 1083
0101 1000 0110 (586)
+ 0100 1001 0111 (497)
---------------
Digit 0: 0110 + 0111 = 1101 (13) > 9 → +0110 = 1 0011 → digit 3, carry 1
Digit 1: 1000 + 1001 + 1 = 1 0010 → carry-out → +0110: 0010 + 0110 = 1000 → digit 8, carry 1
Digit 2: 0101 + 0100 + 1 = 1010 (10) > 9 → +0110 = 1 0000 → digit 0, carry 1
Final carry becomes a new digit: 0001
Result: 0001 0000 1000 0011 = 1083 ✅
10.9 BCD adder in hardware (concept)
A BCD adder uses:
- A 4-bit binary adder for the raw sum.
- A correction detector: it signals a correction when
Carry-out = K + S₃S₂ + S₃S₁(whereKis the carry-out of the first adder andS₃S₂S₁S₀is its sum). This expression is exactly "sum > 9 (1010–1111) or carry-out". - A second 4-bit adder that adds
0110when the detector says so, otherwise0000.
Check of the detector:
- Sums
1010and1011haveS₃S₁ = 1✅;1100–1111haveS₃S₂ = 1✅;0000–1001give 0 ✅.
11. Fixed-Point Number Representation
11.1 Idea
In a fixed-point number, the binary point has a fixed, agreed position in the bit pattern. The point is not stored; both the designer and the hardware simply "know" where it is.
Integer bits Fraction bits
┌─────────────┬─────────────┐
│ b₇ b₆ b₅ b₄ . b₃ b₂ b₁ b₀ │ ← 8 bits with the point after the 4th bit
└─────────────┴─────────────┘
weights: 8 4 2 1 . ½ ¼ ⅛ 1/16
11.2 Q-format notation
Qm.n means m integer bits and n fractional bits. (For signed numbers, the sign bit is counted in m.) Unsigned versions are sometimes written UQm.n.
11.3 Unsigned fixed-point (UQ4.4, 8 bits)
Value = (integer value of all bits) ÷ 2ⁿ
0110 1100 → integer value 108 → 108 ÷ 16 = 6.75
Or by weights: 0110.1100 = 4 + 2 + 0.5 + 0.25 = 6.75 ✅
11.4 Signed fixed-point (2's complement, Q4.4)
The MSB has a negative weight.
1110 0100 → 1110.0100 = −8 + 4 + 2 + 0.25 = −1.75 ✅
Writing a negative value, −5.75 in Q4.4:
- +5.75 =
0101.1100 - Invert all bits:
1010.0011 - Add 1 at the least significant bit (the last fractional place):
1010.0100 - Check: −8 + 2 + 0.25 = −5.75 ✅
11.5 Converting a decimal number to fixed-point
- Multiply by 2ⁿ (n = fractional bits).
- Round to the nearest integer.
- Write it in binary (2's complement if negative).
Example: 3.14159 in UQ4.4
3.14159 × 16 = 50.27 → round to 50 → 0011 0010 = 3 + 0.125 = 3.125
Error ≈ 0.0166. This is quantisation error.
11.6 Resolution and range
| Quantity | Formula | Q4.4 signed | UQ4.4 unsigned |
|---|---|---|---|
| Resolution (smallest step) | 2⁻ⁿ | 0.0625 | 0.0625 |
| Smallest value | −2^(m−1) / 0 | −8 | 0 |
| Largest value | 2^(m−1) − 2⁻ⁿ / 2ᵐ − 2⁻ⁿ | +7.9375 | +15.9375 |
Total bits = m + n. More fraction bits → finer precision but smaller range, and vice versa.
11.7 Arithmetic on fixed-point numbers
Addition and subtraction: when both numbers use the same format, treat them as ordinary integers (the point stays in place). Watch for overflow.
2.5 + 1.25 in Q4.4: 0010.1000 + 0001.0100 = 0011.1100 = 3.75 ✅
Multiplication: multiplying two Qm.n numbers as integers gives a result with 2n fractional bits. Shift right by n to return to the original format.
Example: 2.5 × 1.5 in Q4.4
- 2.5 = 40 (
0010 1000), 1.5 = 24 (0001 1000) (i.e. value × 16) - Integer product: 40 × 24 = 960
- Shift right 4 bits (÷ 16): 960 ÷ 16 = 60 =
0011 1100= 3.75 ✅
Division: shift the dividend left by n before dividing, so the quotient keeps the right scaling.
11.8 Pros and cons
| ✅ Advantages | ❌ Disadvantages |
|---|---|
| Simple, fast hardware (uses integer arithmetic) | Limited range |
| Uniform precision (constant resolution) | Precision is fixed; very small or very large values suffer |
| Predictable behaviour; cheap on small processors | Manual scaling and overflow management |
| Exact for sums of powers of ½ | Many decimal fractions (e.g. 0.1) are only approximate |
Typical uses: embedded systems, digital signal processing (DSP), and low-cost devices without floating-point hardware.
12. Introduction to Floating-Point Representation
12.1 Why floating-point?
Fixed-point cannot cover both huge (e.g. 6.02 × 10²³) and tiny (e.g. 1.6 × 10⁻¹⁹) values in a small number of bits. Floating-point lets the binary point "float" by storing a scale factor (exponent), just like scientific notation.
Decimal scientific: −6.25 × 10³
Binary floating-point: (−1)^sign × 1.mantissa × 2^exponent
12.2 General form
Value = (−1)ˢ × M × 2ᴱ
| Part | Meaning |
|---|---|
| S (sign) | 0 = positive, 1 = negative |
| M (mantissa / significand) | The significant digits (precision) |
| E (exponent) | The power of 2 (scale / range) |
12.3 Normalisation
A floating-point number is normalised when the mantissa has the form 1.xxxx (exactly one non-zero bit before the point).
110.1₂ = 1.101 × 2² (move the point left 2 places → exponent +2)
0.011₂ = 1.1 × 2⁻² (move the point right 2 places → exponent −2)
Since the leading digit of a normalised binary number is always 1, it need not be stored. It is a hidden (implied) bit, which gives one extra bit of precision for free.
12.4 IEEE 754 standard
The universal standard for floating-point.
| Format | Total bits | Sign | Exponent | Fraction (stored) | Bias |
|---|---|---|---|---|---|
| Single precision (float) | 32 | 1 | 8 | 23 | 127 |
| Double precision (double) | 64 | 1 | 11 | 52 | 1023 |
Single precision (32 bits)
┌───┬──────────────┬─────────────────────────┐
│ S │ Exponent(8) │ Fraction(23) │
└───┴──────────────┴─────────────────────────┘
31 30 … 23 22 … 0
Biased exponent: the stored exponent is E + bias, so the exponent field is always a positive (unsigned) number and comparisons are easy.
- Single: stored exponent = true exponent + 127.
Value of a normalised number (single precision):
Value = (−1)ˢ × 1.fraction × 2^(stored exponent − 127)
12.5 Example 1: Encode 6.5 (single precision)
6.5 = 110.1₂- Normalise:
1.101 × 2² - Sign = 0
- Stored exponent = 2 + 127 = 129 =
10000001 - Fraction = bits after the point:
101followed by zeros →101 0000 0000 0000 0000 0000 - Result:
0 | 10000001 | 10100000000000000000000
= 0100 0000 1101 0000 0000 0000 0000 0000 = 0x40D00000
12.6 Example 2: Encode −0.75
0.75 = 0.11₂ = 1.1 × 2⁻¹- Sign = 1
- Stored exponent = −1 + 127 = 126 =
01111110 - Fraction =
1000...0 - Result:
1 | 01111110 | 10000000000000000000000= 0xBF400000
12.7 Example 3: Decode 0 10000010 01001000000000000000000
- Sign = 0 → positive
- Stored exponent = 130 → true exponent = 130 − 127 = 3
- Mantissa =
1.01001₂ - Value =
1.01001 × 2³ = 1010.01₂ = 10.25✅
12.8 Special values (single precision)
| Exponent field | Fraction field | Meaning |
|---|---|---|
| All 0s | All 0s | ±0 |
| All 0s | Non-zero | Subnormal (denormal) numbers: (−1)ˢ × 0.fraction × 2⁻¹²⁶ (fills the gap near zero) |
| All 1s | All 0s | ±Infinity (result of overflow or division by zero) |
| All 1s | Non-zero | NaN (Not a Number, e.g. 0/0) |
| 1 to 254 | Anything | Normal numbers |
12.9 Range and precision
| Format | Approx. smallest normal | Approx. largest | Decimal precision |
|---|---|---|---|
| Single (32-bit) | 1.18 × 10⁻³⁸ | 3.4 × 10³⁸ | about 7 digits |
| Double (64-bit) | 2.2 × 10⁻³⁰⁸ | 1.8 × 10³⁰⁸ | about 15–16 digits |
12.10 Overflow and underflow in floating-point
- Overflow: the magnitude is larger than the largest representable value → result becomes ±∞.
- Underflow: the magnitude is smaller than the smallest normal value → result becomes a subnormal number or 0.
12.11 Rounding errors
Many decimal values (like 0.1) have endless binary expansions and must be rounded, so floating-point results can be slightly inexact. Because of this, two floating-point numbers should usually be compared with a small tolerance, not tested for exact equality.
12.12 Floating-point addition (outline)
- Align the exponents (shift the smaller number's mantissa right).
- Add or subtract the mantissas.
- Normalise the result.
- Round and check for overflow/underflow.
12.13 Fixed-point vs floating-point
| Feature | Fixed-point | Floating-point |
|---|---|---|
| Point position | Fixed | Moves (set by exponent) |
| Range | Small | Very large |
| Precision | Uniform (same step everywhere) | Relative (finer near zero, coarser for large values) |
| Hardware | Simple, fast, cheap | More complex |
| Typical use | Embedded, DSP | Scientific, graphics, general computing |
📝 Quick Revision Cheat Sheet
| Topic | Remember this |
|---|---|
| Addition | 1+1 = 0 carry 1; 1+1+1 = 1 carry 1 |
| Subtraction | 0−1 needs a borrow; or use A + (2's comp of B) |
| Multiplication | Shift and add partial products; product up to m + n bits |
| Division | Binary long division: quotient bit 1 if divisor fits |
| Shifts | Left shift ×2ᵏ, right shift ÷2ᵏ |
| 1's complement | Invert all bits |
| 2's complement | Invert + 1 (or copy up to first 1, invert the rest) |
| 2's complement subtraction | Carry → positive (drop carry); no carry → negative (take 2's comp) |
| 1's complement subtraction | Carry → add it back (end-around carry); no carry → negative |
| Signed magnitude | MSB sign, rest magnitude; has +0 and −0 |
| 2's complement value | MSB weight is −2ⁿ⁻¹ |
| Unsigned range | 0 to 2ⁿ − 1 |
| 2's complement range | −2ⁿ⁻¹ to 2ⁿ⁻¹ − 1 |
| SM / 1's complement range | −(2ⁿ⁻¹ − 1) to 2ⁿ⁻¹ − 1 |
| Signed overflow | Carry into MSB ⊕ carry out of MSB |
| Unsigned overflow | Carry out of MSB |
| Overflow impossible when | Adding a positive and a negative number |
| Sign extension | 2's/1's complement: copy MSB; unsigned: pad 0s |
| BCD addition fix | Add 0110 if group > 9 or carry out |
| BCD subtraction | Add the 10's complement (9's comp + 1) |
| Fixed-point Qm.n | m integer bits, n fraction bits; resolution 2⁻ⁿ |
| Fixed-point multiply | Multiply as integers, then shift right n |
| IEEE 754 single | 1 + 8 + 23 bits, bias 127 |
| IEEE 754 double | 1 + 11 + 52 bits, bias 1023 |
| Normalised mantissa | 1.xxxx (leading 1 hidden) |
| Special values | Exp all 1s: ∞ or NaN; exp all 0s: 0 or subnormal |
🧠 Practice Questions
- Add
10110and01101. - Subtract
01101from11010. - Find the 8-bit 2's complement representation of −100.
- Multiply
1101by011. - Divide
100101by110; give the quotient and remainder. - State the range of a 6-bit number in unsigned, signed magnitude and 2's complement forms.
- Add
01100100and01100100in 8-bit 2's complement. Does overflow occur? - Sign-extend the 5-bit 2's complement number
10110to 8 bits. - Add the BCD numbers 479 and 385.
- Represent −5.75 in signed Q4.4 format (2's complement).
- Write 10.25 in IEEE 754 single-precision (hex).
- Using 5-bit 2's complement, compute 9 − 12.
- What is the decimal value of
1011as unsigned, signed magnitude, 1's complement and 2's complement?
Click for answers
- 22 + 13 = 35 → 100011
- 26 − 13 = 13 → 01101
- +100 =
01100100→ invert10011011→ +1 → 10011100 - 13 × 3 = 39 → 100111
- 37 ÷ 6 → quotient 110 (6), remainder 1
- Unsigned 0 to 63; signed magnitude −31 to +31; 2's complement −32 to +31
- 100 + 100 = 200 →
11001000, which reads as −56 in 2's complement. Carry into MSB = 1, carry out = 0 → overflow. 10110= −16 + 4 + 2 = −10 → sign-extend → 11110110 (= −10 ✅)- 479 + 385 = 864; BCD:
0100 0111 1001 + 0011 1000 0101: digit 0: 1001 + 0101 = 1110 → +0110 → 0100, carry 1; digit 1: 0111 + 1000 + 1 = 1 0000 → +0110 → 0110, carry 1; digit 2: 0100 + 0011 + 1 = 1000 → result 1000 0110 0100 - +5.75 =
0101.1100→ invert1010.0011→ +1 →1010.0100 - 10.25 =
1010.01= 1.01001 × 2³; exponent = 130 =10000010; bits0 10000010 01001000...0= 0x41240000 - 9 =
01001; 12 =01100→ 2's complement10100;01001 + 10100 = 11101(no carry) → negative; magnitude = 2's complement of11101=00011→ −3 (and11101= −16 + 8 + 4 + 1 = −3 ✅) - Unsigned 11; signed magnitude −3; 1's complement −4; 2's complement −5
##Codes and Error Detection#
Friendly, structured notes for Unit 4: Codes and Error Detection. Read in order the first time. Each idea has a worked example, and a cheat sheet and practice questions are at the end.
📑 Table of Contents
- Weighted and Non-Weighted Codes
- Self-Complementing Codes
- Gray Code Applications
- Parity Bits and Parity Checking
- Even and Odd Parity
- Hamming Distance
- Hamming Code
- Error Detection vs Error Correction
- Checksum and CRC Fundamentals
- Applications of Coding in Digital Systems
- Quick Revision Cheat Sheet
🧭 Big Picture
A code is a systematic way of representing information (a digit, a letter, a position, a message) as a pattern of bits. Codes are used for two broad purposes:
| Purpose | Question it answers | Examples |
|---|---|---|
| Representation codes | How should I write this information in bits? | BCD, 8421, 2421, Excess-3, Gray |
| Error-control codes | How do I know if the bits were damaged, and can I repair them? | Parity, Hamming, checksum, CRC |
Data ──► ENCODER ──► [ code word ] ──► NOISY CHANNEL / STORAGE ──► [ received word ] ──► DECODER ──► Data
(adds check bits) (bits may flip: 0↔1) (checks / corrects)
Handy terms
| Term | Meaning |
|---|---|
| Code word | A valid bit pattern of a code |
| Data (message) bits | The useful information bits (often written m or k) |
| Check (redundant) bits | Extra bits added only to detect or correct errors |
| Redundancy | The extra bits beyond what the information needs |
| Code length (n) | Total bits = data bits + check bits |
| Code rate | Data bits ÷ total bits (e.g. 4/7); closer to 1 means less overhead |
| Bit error | A bit that changed value (0 → 1 or 1 → 0) during transmission or storage |
| Single-bit error | Exactly one bit flipped |
| Burst error | Several consecutive bits damaged together |
1. Weighted and Non-Weighted Codes
1.1 Weighted codes
In a weighted code, each bit position has a fixed weight. The decimal value of a code word is the sum of the weights of the positions holding a 1.
| Code | Weights | Example |
|---|---|---|
| 8421 (natural BCD) | 8, 4, 2, 1 | 0111 = 4 + 2 + 1 = 7 |
| 2421 | 2, 4, 2, 1 | 1101 = 2 + 4 + 0 + 1 = 7 |
| 5421 | 5, 4, 2, 1 | 1010 = 5 + 0 + 2 + 0 = 7 |
| 84-2-1 | 8, 4, −2, −1 | 1001 = 8 + 0 + 0 − 1 = 7 |
Notice: the same digit (7) has a different code in each weighted system, because the weights differ.
1.2 Table of common 4-bit weighted codes
| Digit | 8421 | 2421 | 5421 | 84-2-1 |
|---|---|---|---|---|
| 0 | 0000 | 0000 | 0000 | 0000 |
| 1 | 0001 | 0001 | 0001 | 0111 |
| 2 | 0010 | 0010 | 0010 | 0110 |
| 3 | 0011 | 0011 | 0011 | 0101 |
| 4 | 0100 | 0100 | 0100 | 0100 |
| 5 | 0101 | 1011 | 1000 | 1011 |
| 6 | 0110 | 1100 | 1001 | 1010 |
| 7 | 0111 | 1101 | 1010 | 1001 |
| 8 | 1000 | 1110 | 1011 | 1000 |
| 9 | 1001 | 1111 | 1100 | 1111 |
1.3 Non-weighted codes
In a non-weighted code, the bit positions have no fixed weights. You cannot get the value by adding weights. You must use a table or a rule to decode.
| Code | Why it is non-weighted | Main purpose |
|---|---|---|
| Excess-3 | Formed as BCD + 3, so no fixed weights | Decimal arithmetic, self-complementing |
| Gray code | Formed by a reflection rule | One-bit change between steps |
| 2-out-of-5 code | Every code word has exactly two 1s | Error detection |
| ASCII / Unicode | Arbitrary assignments of numbers to characters | Text |
Excess-3 table (recap)
| Digit | 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 |
|---|---|---|---|---|---|---|---|---|---|---|
| XS-3 | 0011 | 0100 | 0101 | 0110 | 0111 | 1000 | 1001 | 1010 | 1011 | 1100 |
2-out-of-5 code (one common assignment)
| Digit | 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 |
|---|---|---|---|---|---|---|---|---|---|---|
| Code | 00110 | 00011 | 00101 | 01001 | 01010 | 01100 | 10001 | 10010 | 10100 | 11000 |
Any received word that does not contain exactly two 1s must contain an error. This is a built-in error check.
1.4 Other useful ways to classify codes
| Property | Meaning | Example |
|---|---|---|
| Sequential code | Each code word is obtained from the previous one by adding 1 | 8421, Excess-3 |
| Unit-distance (cyclic) code | Consecutive code words differ in exactly one bit | Gray |
| Self-complementing code | Inverting the bits gives the 9's complement | 2421, Excess-3 (Section 2) |
| Constant-weight code | Every code word has the same number of 1s | 2-out-of-5 |
| Error-detecting code | Some bit patterns are deliberately invalid, so errors can be noticed | 2-out-of-5, parity codes |
1.5 Weighted vs non-weighted
| Feature | Weighted | Non-weighted |
|---|---|---|
| Value from bits | Sum of weights of the 1s | Needs a table or a rule |
| Ease of conversion to decimal | Easy | Harder |
| Examples | 8421, 2421, 5421, 84-2-1 | Excess-3, Gray, 2-out-of-5 |
2. Self-Complementing Codes
2.1 Definition
A code is self-complementing if the 9's complement of a decimal digit is obtained by simply inverting every bit (taking the 1's complement) of its code word.
9's complement of digit d = 9 − d
2.2 Example: the 2421 code
| Digit | Code | Invert bits | Decoded as | 9 − digit |
|---|---|---|---|---|
| 0 | 0000 | 1111 | 9 | 9 ✅ |
| 2 | 0010 | 1101 | 7 | 7 ✅ |
| 3 | 0011 | 1100 | 6 | 6 ✅ |
| 4 | 0100 | 1011 | 5 | 5 ✅ |
The property holds for all digits, so the table is symmetric: the codes for 5–9 are the bit-inversions of the codes for 4–0.
2.3 Counter-example: 8421 is not self-complementing
Digit 3 = 0011. Invert → 1100 = 12, which is not even a valid BCD digit. The 9's complement of 3 should be 6 (0110). ❌
2.4 Which codes are self-complementing?
| Code | Weights sum / type | Self-complementing? |
|---|---|---|
| 2421 | 2 + 4 + 2 + 1 = 9 | ✅ Yes |
| 84-2-1 | 8 + 4 − 2 − 1 = 9 | ✅ Yes |
| 5211 | 5 + 2 + 1 + 1 = 9 | ✅ Yes (with the right assignment) |
| Excess-3 | Non-weighted | ✅ Yes |
| 8421 | 8 + 4 + 2 + 1 = 15 | ❌ No |
| 5421 | 5 + 4 + 2 + 1 = 12 | ❌ No |
📌 Rule for weighted codes: a necessary condition is that the weights add up to 9. (Then the code words can be chosen so that inversion maps d to 9 − d.)
Why the sum must be 9: inverting all four bits of a word gives value (sum of all weights) − (original value). For that to equal 9 − d, the sum of the weights must be 9.
A 5211 assignment that works
| Digit | 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 |
|---|---|---|---|---|---|---|---|---|---|---|
| 5211 | 0000 | 0001 | 0011 | 0101 | 0111 | 1000 | 1010 | 1100 | 1110 | 1111 |
Check: 0011 (2) inverts to 1100 = 5 + 2 = 7 ✅; 0101 (3) inverts to 1010 = 5 + 1 = 6 ✅.
2.5 Excess-3 as a self-complementing code
Digit 2 = 0101. Invert → 1010 = 7 ✅ (9 − 2). Digit 4 = 0111. Invert → 1000 = 5 ✅.
2.6 Telltale pattern
In a self-complementing code the MSB is 0 for digits 0–4 and 1 for digits 5–9. The two halves are mirror images, so a digit and its 9's complement have opposite MSBs.
2.7 Why are they useful?
They make subtraction by 9's complement very easy in decimal arithmetic circuits. No special circuit is needed to find 9 − d; simple inverters do it.
Example: 8 − 3 using 9's complement in the 2421 code
- 3 =
0011. Invert →1100= 6 (the 9's complement of 3). - Add: 8 + 6 = 14 → there is a carry out of the digit.
- End-around carry: the carry (1) is added back to the sum: 4 + 1 = 5 ✅
3. Gray Code Applications
3.1 Quick recap of the Gray code
- A unit-distance code: moving to the next number changes exactly one bit.
- The sequence is cyclic: the last word also differs by one bit from the first.
- Binary → Gray:
G = B ⊕ (B shifted right by one bit). The MSB is copied; each other Gray bit = this bit XOR the previous bit. - Gray → Binary: the MSB is copied; each next binary bit = the previous binary bit XOR this Gray bit.
| Decimal | 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 |
|---|---|---|---|---|---|---|---|---|
| Binary | 000 | 001 | 010 | 011 | 100 | 101 | 110 | 111 |
| Gray | 000 | 001 | 011 | 010 | 110 | 111 | 101 | 100 |
3.2 The core problem Gray code solves
In ordinary binary, many bits can change at once: for example 011 → 100 flips all three bits. In real hardware the bits never switch at exactly the same instant. For a short moment the system may see a wrong intermediate value:
Binary 011 → 100 : possible glitch values on the way
011 → 111 (7) or 011 → 000 (0) or 011 → 101 ... (wrong readings!)
Gray 010 → 110 : only ONE bit changes, so the reading is either 3 (old) or 4 (new)
With Gray code, the worst error is being off by one step, never a wild jump.
3.3 Application 1: Rotary and linear position encoders ⭐
- A shaft encoder is a disc with concentric tracks of conducting or transparent segments; sensors read the pattern to find the angle.
- If the disc used binary patterns, a sensor sitting at a boundary could misread several bits and report a completely wrong angle.
- With a Gray-coded disc, a boundary crossing changes only one track, so the reading is always the old or the new position.
- Used in robotics, machine tools, volume knobs, steering-angle sensors, and positioning systems.
3.4 Application 2: Karnaugh maps (K-maps)
Rows and columns of a K-map are labelled in Gray-code order (00, 01, 11, 10), so adjacent cells differ in exactly one variable. That is what lets you group neighbouring 1s and simplify Boolean expressions.
BC
00 01 11 10 ← Gray order, NOT binary order
A=0 [ ][ ][ ][ ]
A=1 [ ][ ][ ][ ]
3.5 Application 3: Counters and low switching activity
- Counting 0 → 15 in binary flips a total of 26 bits over the 15 steps.
- Counting 0 → 15 in Gray flips only 15 bits (one per step).
- Fewer transitions mean less power consumption, less electrical noise, and fewer chances of glitches in logic that decodes the count.
3.6 Application 4: Passing counters between clock domains
When a counter value (such as a FIFO read/write pointer) must be sent to a part of the circuit running on a different, unrelated clock, a binary counter could be sampled mid-change and give a bad value. A Gray-coded pointer changes one bit at a time, so the sampled value is always valid or off by only one.
3.7 Application 5: Analog-to-digital conversion and error minimisation
- Some analog-to-digital converters and position-to-digital systems output Gray code so that a slightly noisy input near a threshold causes only a one-bit error.
- In digital communication, mapping bit patterns to signal levels in Gray order means a small signal error (landing in a neighbouring level) causes only a one-bit error.
3.8 Summary table
| Application | Why Gray code helps |
|---|---|
| Shaft / position encoders | No wild misreads at segment boundaries |
| K-map labelling | Adjacent cells differ in one variable |
| Counters | Fewer bit transitions → low power and noise |
| Clock-domain crossing (FIFO pointers) | Sampled value is never wildly wrong |
| ADC / communication mappings | A neighbouring-level error costs just one bit |
4. Parity Bits and Parity Checking
4.1 What is a parity bit?
A parity bit is one extra bit added to a group of data bits so that the total number of 1s in the group (including the parity bit) is either even or odd, as agreed beforehand. It is the simplest error-detecting code.
Data bits (n) Parity bit
┌──────────────┐ ┌───┐
│ d₆ d₅ ... d₀ │ + │ P │ → transmitted as one (n+1)-bit word
└──────────────┘ └───┘
The parity bit is usually placed as the MSB or LSB of the word. Transmitter and receiver must agree on where.
4.2 The process
Transmitter Receiver
─────────── ────────
data ──► PARITY GENERATOR received word ──► PARITY CHECKER
(computes P) (counts the 1s)
data + P ───── channel ─────────────► OK → accept
BAD → error flagged (ask for resend / discard)
4.3 Generating the parity bit (XOR logic)
The XOR of bits is 1 when the number of 1s is odd. So:
- Even parity bit:
P = D₀ ⊕ D₁ ⊕ D₂ ⊕ ... ⊕ Dₙ₋₁ - Odd parity bit:
P = ¬(D₀ ⊕ D₁ ⊕ ... ⊕ Dₙ₋₁)(complement of the even-parity bit)
4.4 Checking at the receiver
XOR all received bits including the parity bit.
- Even parity system: result 0 → no error detected; result 1 → error.
- Odd parity system: result 1 → no error detected; result 0 → error.
4.5 Example: even parity on ASCII 'A'
'A' = 1000001 (7 bits) has two 1s (already even) → parity bit = 0.
Transmitted (parity as MSB): 0 1000001 = 01000001.
Example: 'C' = 1000011 has three 1s (odd) → parity bit = 1 → 11000011.
4.6 Example: detecting an error
Sent (even parity): 01000001. One bit flips on the way → received 01001001.
Count the 1s: three → odd → ❌ error detected.
4.7 What parity can and cannot do
| ✅ Can | ❌ Cannot |
|---|---|
| Detect any single-bit error | Correct the error (does not know which bit is wrong) |
| Detect any odd number of bit errors (1, 3, 5, ...) | Detect an even number of errors (2, 4, ...), because they cancel out |
| Very cheap: 1 extra bit, one XOR tree | Detect which word is wrong in a long stream if errors cluster in pairs |
Example of an undetected error (even parity): sent 01000001; two bits flip and it arrives as 01010011. The received word has four 1s, which is still an even count, so the checker says "OK" even though the data is wrong.
4.8 Two-dimensional (block) parity
Arrange words in a rectangle, add a parity bit to each row and a parity word for each column. This can locate and correct a single-bit error.
Data rows (even parity):
Data bits Row parity
1 0 1 1 | 1
0 1 1 0 | 0
1 1 0 0 | 0
----------+------
0 0 0 1 | 1 ← column parities (and a parity of parities)
Now suppose the bit in row 2, column 3 flips (1 → 0):
1 0 1 1 | 1 row 1: OK
0 1 0 0 | 0 row 2: only one 1 → ODD → row 2 is wrong
1 1 0 0 | 0 row 3: OK
---------+---
0 0 0 1 | 1 column 3: bits 1,0,0,0 → ODD → column 3 is wrong
The failing row (2) and the failing column (3) intersect at the damaged bit → flip it back ✅. Two errors can be detected but not always corrected.
5. Even and Odd Parity
5.1 Definitions
| Type | Rule |
|---|---|
| Even parity | The total number of 1s (data + parity bit) is even |
| Odd parity | The total number of 1s (data + parity bit) is odd |
5.2 Parity bit table (3-bit data)
| Data (D₂D₁D₀) | Number of 1s | Even-parity bit | Word with even parity | Odd-parity bit | Word with odd parity |
|---|---|---|---|---|---|
| 000 | 0 | 0 | 0 000 | 1 | 1 000 |
| 001 | 1 | 1 | 1 001 | 0 | 0 001 |
| 010 | 1 | 1 | 1 010 | 0 | 0 010 |
| 011 | 2 | 0 | 0 011 | 1 | 1 011 |
| 100 | 1 | 1 | 1 100 | 0 | 0 100 |
| 101 | 2 | 0 | 0 101 | 1 | 1 101 |
| 110 | 2 | 0 | 0 110 | 1 | 1 110 |
| 111 | 3 | 1 | 1 111 | 0 | 0 111 |
Notice: the odd-parity bit is always the complement of the even-parity bit.
5.3 Quick method
- Count the 1s in the data.
- Even parity: if the count is odd → parity bit = 1; if even → 0.
- Odd parity: if the count is even → parity bit = 1; if odd → 0.
5.4 Even vs odd: which is used?
Both detect exactly the same errors (all odd-numbered bit errors). The choice is a convention set by the system design. A small practical edge for odd parity:
- With odd parity, a word of all 0s is never valid. If a line is dead or the power fails and everything reads 0, the checker sees an error. (With even parity, all 0s with P = 0 would look valid.)
5.5 Checking practice (even parity, 4 data bits + 1 parity bit)
| Received | Number of 1s | Verdict |
|---|---|---|
| 10100 | 2 | ✅ OK (even) |
| 11101 | 4 | ✅ OK (even) |
| 01110 | 3 | ❌ Error (odd) |
| 11111 | 5 | ❌ Error (odd) |
5.6 Parity in practice
- Serial communication (UART) lets you choose even, odd or no parity for each character.
- Memory words can carry a parity bit per byte to detect corrupted storage.
- Wherever a quick, cheap check for single-bit errors is enough.
6. Hamming Distance
6.1 Definition
The Hamming distance between two binary words of the same length is the number of bit positions in which they differ.
How to compute: XOR the two words and count the 1s in the result.
Example: 10110 and 11100
10110
⊕ 11100
-------
01010 → two 1s → Hamming distance = 2
6.2 Hamming weight
The Hamming weight of a word is the number of 1s in it. (So distance(a, b) = weight(a ⊕ b), and the distance from the all-zero word equals the weight.)
6.3 Minimum distance of a code
For a code (a set of valid code words), the minimum Hamming distance d_min is the smallest distance between any two different valid code words.
Example: code = { 00000, 01011, 10101, 11110 }
| Pair | XOR | Distance |
|---|---|---|
| 00000, 01011 | 01011 | 3 |
| 00000, 10101 | 10101 | 3 |
| 00000, 11110 | 11110 | 4 |
| 01011, 10101 | 11110 | 4 |
| 01011, 11110 | 10101 | 3 |
| 10101, 11110 | 01011 | 3 |
d_min = 3
6.4 Why distance matters: error-control power
Errors move a received word away from the transmitted code word. The larger the minimum distance between valid code words, the more bit errors it takes to turn one valid word into another.
For a code with minimum distance d_min:
| Ability | Formula |
|---|---|
| Detect up to this many bit errors | d_min − 1 |
| Correct up to this many bit errors | ⌊(d_min − 1) / 2⌋ |
| Correct t errors and detect s ≥ t errors at once | d_min ≥ t + s + 1 |
| d_min | Detects | Corrects | Example code |
|---|---|---|---|
| 1 | 0 | 0 | Plain binary (every pattern is valid) |
| 2 | 1 | 0 | Single parity bit |
| 3 | 2 | 1 | Hamming code, 3× repetition |
| 4 | 3 | 1 (and detects 2 together) | Extended Hamming (SEC-DED) |
| 5 | 4 | 2 | Stronger codes |
6.5 Picture: spheres around code words
Imagine each valid code word as a point, with a "bubble" of radius t around it containing all words within distance t. If bubbles do not overlap, any received word inside a bubble can be corrected back to the centre.
d_min = 3 (valid words: 000 and 111)
000 ●─────○─────○─────● 111
1 flip 2 flips
Received 010 (distance 1 from 000, distance 2 from 111)
→ nearest valid word is 000 → corrected to 000 ✅
6.6 Example: 3× repetition code (d_min = 3)
Send each bit three times: 0 → 000, 1 → 111.
- Received
010: one 1 and two 0s → majority vote → decoded as 0 ✅ (1 error corrected). - Received
011: majority is 1 → decoded as 1, but if the original were000with two errors this decoding is wrong. A d_min = 3 code cannot correct 2 errors.
6.7 Nearest-neighbour (minimum-distance) decoding
Rule: decode a received word as the valid code word nearest to it (smallest Hamming distance). If several are equally near, the error can only be detected, not corrected.
6.8 Links to earlier ideas
- Gray code: consecutive code words have distance 1.
- Single parity code: every valid word has the same parity, so two valid words differ in an even number of bits; hence d_min = 2.
- 2-out-of-5 code: two valid words differ in an even number of positions, so d_min = 2.
7. Hamming Code
7.1 What is it?
The Hamming code (R. W. Hamming, 1950) is a single-error-correcting code. It places several parity bits at special positions, each checking a different overlapping set of bits. When an error occurs, the pattern of failed checks points directly at the bad bit position.
It has minimum distance d_min = 3, so it can correct 1 error (or detect 2).
7.2 How many check bits?
For m data bits and r check bits, the check bits must be able to describe "no error" plus an error in any of the m + r positions:
2ʳ ≥ m + r + 1
| Data bits (m) | Check bits (r) | Total (n = m + r) | Notation (n, m) |
|---|---|---|---|
| 4 | 3 | 7 | (7, 4) |
| 7 | 4 | 11 | (11, 7) |
| 8 | 4 | 12 | (12, 8) |
| 11 | 4 | 15 | (15, 11) |
| 16 | 5 | 21 | (21, 16) |
| 26 | 5 | 31 | (31, 26) |
| 32 | 6 | 38 | (38, 32) |
Check (m = 8): r = 3 → 8 ≥ 12? ❌; r = 4 → 16 ≥ 13 ✅ → r = 4.
Code rate improves as the block gets longer: 4/7 ≈ 0.57, 11/15 ≈ 0.73, 26/31 ≈ 0.84.
7.3 Bit positions
Number the bits from 1, starting at the left.
- Check (parity) bits go at positions that are powers of 2: 1, 2, 4, 8, 16, ...
- Data bits fill all the remaining positions: 3, 5, 6, 7, 9, 10, 11, ...
Position: 1 2 3 4 5 6 7
Role: P1 P2 D1 P4 D2 D3 D4 ← (7,4) layout
Position: 1 2 3 4 5 6 7 8 9 10 11 12
Role: P1 P2 D1 P4 D2 D3 D4 P8 D5 D6 D7 D8 ← (12,8) layout
7.4 Which bits does each parity bit check?
Write each position number in binary. Parity bit Pₖ checks every position whose binary form has a 1 in the same bit place as Pₖ.
| Position | Binary (4 bits) |
|---|---|
| 1 | 0001 |
| 2 | 0010 |
| 3 | 0011 |
| 4 | 0100 |
| 5 | 0101 |
| 6 | 0110 |
| 7 | 0111 |
| Parity bit | Checks positions | Rule |
|---|---|---|
| P1 | 1, 3, 5, 7, 9, 11, ... | Positions with the 1s bit set |
| P2 | 2, 3, 6, 7, 10, 11, ... | Positions with the 2s bit set |
| P4 | 4, 5, 6, 7, 12, 13, ... | Positions with the 4s bit set |
| P8 | 8–15, 24–31, ... | Positions with the 8s bit set |
Each parity bit is chosen so that its group (including itself) has even parity (using even parity throughout).
💡 Why powers of 2? Each position's binary number is unique, so every bit is covered by a unique combination of parity checks. That unique combination is exactly its address.
7.5 Encoding example: data 1011 → (7,4) Hamming code (even parity)
- Place data at positions 3, 5, 6, 7: D1 = 1, D2 = 0, D3 = 1, D4 = 1
Position: 1 2 3 4 5 6 7
Bit: ? ? 1 ? 0 1 1
- P1 (positions 1, 3, 5, 7): bits 3, 5, 7 = 1, 0, 1 → two 1s → P1 = 0
- P2 (positions 2, 3, 6, 7): bits 3, 6, 7 = 1, 1, 1 → three 1s → P2 = 1
- P4 (positions 4, 5, 6, 7): bits 5, 6, 7 = 0, 1, 1 → two 1s → P4 = 0
Code word (positions 1 to 7): 0 1 1 0 0 1 1 = 0110011 ✅
7.6 Decoding and error correction: the syndrome
At the receiver, recompute each check over its group including the received parity bit:
- C1 = XOR of positions 1, 3, 5, 7
- C2 = XOR of positions 2, 3, 6, 7
- C4 = XOR of positions 4, 5, 6, 7
Each check is 0 if its group has even parity (OK) and 1 if it fails. Read them as a binary number C4 C2 C1, called the syndrome.
Syndrome = 000 → no error. Otherwise, the syndrome (in decimal) is the position of the wrong bit → flip that bit.
7.7 Error example 1: error in a data bit
Sent 0110011. Bit at position 6 flips (1 → 0) → received 0110001.
| Check | Positions | Bits | 1s | Result |
|---|---|---|---|---|
| C1 | 1, 3, 5, 7 | 0, 1, 0, 1 | 2 | 0 (OK) |
| C2 | 2, 3, 6, 7 | 1, 1, 0, 1 | 3 | 1 (fail) |
| C4 | 4, 5, 6, 7 | 0, 0, 0, 1 | 1 | 1 (fail) |
Syndrome C4 C2 C1 = 110 = 6 → the error is at position 6 → flip it → 0110011 ✅. Data bits are positions 3, 5, 6, 7 → 1011 ✅
7.8 Error example 2: error in a parity bit
Sent 0110011. Position 4 flips (0 → 1) → received 0111011.
Only C4 fails (C1 = 0, C2 = 0, C4 = 1) → syndrome 100 = 4 → flip position 4 ✅. Parity bits are corrected just like data bits.
7.9 Summary of the procedure
| Step | Encoder | Decoder |
|---|---|---|
| 1 | Mark positions 1, 2, 4, 8... as parity positions | Recompute every check C1, C2, C4, ... |
| 2 | Put data bits in the other positions | Form the syndrome from the failed checks |
| 3 | Set each parity bit for even parity of its group | Syndrome = 0 → accept; else flip the bit at that position |
| 4 | Send the code word | Extract the data bits |
7.10 Parity-check matrix view (concise)
For the (7,4) code, the columns of the check matrix H are simply the binary numbers 1 to 7:
pos: 1 2 3 4 5 6 7
C4 : 0 0 0 1 1 1 1
C2 : 0 1 1 0 0 1 1
C1 : 1 0 1 0 1 0 1
Syndrome S = H · (received word) (XOR arithmetic). The syndrome equals the column of H that matches the error position, which is why the syndrome is the position number.
7.11 Extended Hamming code (SEC-DED)
Add one more overall parity bit covering the whole word. The code then becomes Single-Error-Correcting, Double-Error-Detecting (SEC-DED) with d_min = 4. Example: (8,4), (72,64) used in memory.
| Syndrome | Overall parity check | Meaning | Action |
|---|---|---|---|
| 000 | OK | No error | Accept |
| ≠ 000 | Fails | Single error | Correct it |
| 000 | Fails | Error in the overall parity bit itself | Correct that bit |
| ≠ 000 | OK | Double error | Detect only, cannot correct |
7.12 Limits of the basic Hamming code
- It assumes at most one error per word. With two errors, it may "correct" the wrong bit and produce incorrect data.
- It is best when errors are random and rare, not in long bursts.
8. Error Detection vs Error Correction
8.1 Error detection
Detection only tells you that an error exists. The receiver cannot repair it. It must discard the data or ask for it again.
8.2 Error correction
Correction finds which bits are wrong and fixes them using only the received information. It needs more redundancy.
8.3 Comparison
| Feature | Error detection | Error correction |
|---|---|---|
| Goal | Know that data is damaged | Know and repair the damage |
| Redundancy needed | Small | Larger |
| Min distance needed (t errors) | d_min ≥ t + 1 | d_min ≥ 2t + 1 |
| Receiver action | Reject / request resend | Fix bits automatically |
| Complexity | Simple (parity, checksum, CRC) | Higher (Hamming, etc.) |
| Needs a return channel | Often yes (to request retransmission) | No |
| Typical examples | Parity, checksum, CRC | Hamming code, repetition code |
8.4 Two basic strategies
1. ARQ (Automatic Repeat reQuest): detect and retransmit
Sender ──► data + check ──► Receiver
Sender ◄── ACK (OK) or NAK (error: please resend) ◄── Receiver
- Good when there is a two-way link, errors are infrequent, and a resend is cheap.
2. FEC (Forward Error Correction): correct without asking again
- Check bits let the receiver fix errors on its own.
- Good when resending is impossible or too slow: one-way broadcast, deep-space or satellite links, memory and storage.
Many real systems combine the two: correct the common small errors, and detect the bigger ones to request a resend.
8.5 Types of errors
| Type | Description |
|---|---|
| Single-bit error | Only one bit in the word is changed |
| Multiple-bit error | Two or more non-adjacent bits are changed |
| Burst error | A run of consecutive bits is corrupted (common in real channels due to interference or scratches) |
8.6 Which technique fits which job?
| Technique | Detects | Corrects | Overhead | Best for |
|---|---|---|---|---|
| Single parity bit | Any odd number of bit errors | ❌ | 1 bit per word | Simple low-cost checks |
| Two-dimensional parity | Many patterns | ✅ 1 bit | Row and column bits | Small data blocks |
| Repetition code (3×) | Up to 2 errors | ✅ 1 error | Very high (200%) | Very simple/critical signals |
| Hamming code | Up to 2 errors (with SEC-DED) | ✅ 1 error | Moderate | Memory, hardware |
| Checksum | Many random errors | ❌ | 8–32 bits per block | Network headers, files |
| CRC | Most errors and bursts | ❌ (normally) | 8–32 bits per block | Network frames, storage |
8.7 The trade-off
More redundancy = stronger protection but lower efficiency. The designer balances reliability, speed, cost, and bandwidth for the application.
9. Checksum and Cyclic Redundancy Check (CRC) Fundamentals
Both methods compute a short value from a large block of data and send it along. The receiver recomputes it and compares. They are detection methods (they do not repair the data).
9A. Checksum
9A.1 Idea
Treat the data as a series of fixed-size numbers (bytes or words), add them up, and send a function of the sum as the checksum.
9A.2 Method (2's complement checksum, 8-bit)
Sender
- Add all data bytes, keeping only the lowest 8 bits (ignore overflow carries).
- Take the 2's complement of that sum. This is the checksum.
- Send the data followed by the checksum.
Receiver
- Add all received bytes including the checksum (low 8 bits only).
- If the result is 00 → no error detected; otherwise → error.
Example: data bytes 25, 1F, 4A, 3C (hex)
25 + 1F = 44
44 + 4A = 8E
8E + 3C = CA ← sum of the data (8 bits)
Checksum = 100 − CA = 36 (2's complement of CA)
Sent: 25 1F 4A 3C 36
Receiver: CA + 36 = 100 → low 8 bits = 00 ✅ OK
9A.3 Method (1's complement checksum)
Sender: add all bytes using end-around carry (any carry out of the top bit is added back to the bottom), then invert the sum. Receiver: add all bytes including the checksum; the result should be all 1s (FF).
Same data, 1's complement version
Sum = CA (no carry out)
Checksum = invert(CA) = 35
Receiver: CA + 35 = FF ✅ (all ones → OK)
End-around carry example: B5 + 93
B5 + 93 = 148 (9 bits: carry out of 8 bits)
Wrap the carry: 48 + 1 = 49
Checksum = invert(49) = B6
Receiver: 49 + B6 = FF ✅
(The Internet's IP, TCP and UDP headers use this idea with 16-bit words.)
9A.4 Strengths and weaknesses
| ✅ Strengths | ❌ Weaknesses |
|---|---|
| Very simple and fast to compute | Order is ignored: swapping two bytes gives the same sum |
| Small overhead (1 byte or word per block) | Two errors that cancel out (one +1, another −1) go unnoticed |
| Catches most random errors | Weaker than CRC for burst errors |
9B. Cyclic Redundancy Check (CRC)
9B.1 Idea
Treat the whole data block as one very long binary number (a polynomial) and divide it by a fixed generator pattern. The remainder is the CRC. The sender attaches the remainder; the receiver does the division again and expects zero remainder.
9B.2 Modulo-2 arithmetic (no carries, no borrows)
CRC arithmetic uses XOR:
| Operation | Result |
|---|---|
| 0 + 0 = 0 − 0 | 0 |
| 0 + 1 = 1 + 0 = 0 − 1 = 1 − 0 | 1 |
| 1 + 1 = 1 − 1 | 0 |
So addition and subtraction are the same: XOR.
9B.3 Polynomial notation
Bits are the coefficients of a polynomial in x:
1011 ↔ 1·x³ + 0·x² + 1·x¹ + 1·x⁰ = x³ + x + 1
The generator polynomial G(x) of degree r (so G has r + 1 bits) is agreed in advance. The CRC has r bits.
9B.4 CRC procedure (sender)
- Choose the generator G (r + 1 bits).
- Append r zeros to the data.
- Divide that longer bit string by G using modulo-2 division (XOR).
- The r-bit remainder is the CRC.
- Replace the appended zeros with the CRC and transmit (data + CRC).
9B.5 Worked example
Data = 1101, Generator G = 1011 (x³ + x + 1), so r = 3.
Append 3 zeros → dividend 1101000.
| Step | Current bits | Action | Result (XOR) |
|---|---|---|---|
| 1 | 1101 | leading 1 → XOR 1011 | 0110 |
| 2 | 110 + next bit 0 = 1100 | leading 1 → XOR 1011 | 0111 |
| 3 | 111 + next bit 0 = 1110 | leading 1 → XOR 1011 | 0101 |
| 4 | 101 + next bit 0 = 1010 | leading 1 → XOR 1011 | 0001 |
Remainder (last 3 bits) = 001 → CRC = 001.
Transmitted frame = data + CRC = 1101 001 = 1101001
(Check with polynomials: x³·(x³ + x² + 1) = x⁶ + x⁵ + x³; dividing by x³ + x + 1 leaves remainder 1 = 001 ✅.)
9B.6 CRC procedure (receiver)
Divide the whole received frame by the same G.
- Remainder = 0 → no error detected.
- Remainder ≠ 0 → error detected.
Check with the frame 1101001:
| Step | Current bits | Result (XOR with 1011) |
|---|---|---|
| 1 | 1101 | 0110 |
| 2 | 110 + 0 = 1100 | 0111 |
| 3 | 111 + 0 = 1110 | 0101 |
| 4 | 101 + 1 = 1011 | 0000 ✅ |
Remainder 000 → accepted ✅.
With an error: suppose the 4th bit flips and the frame is received as 1100001.
| Step | Current bits | Result (XOR with 1011) |
|---|---|---|
| 1 | 1100 | 0111 |
| 2 | 111 + 0 = 1110 | 0101 |
| 3 | 101 + 0 = 1010 | 0001 |
| 4 | 001 + 1 = 0011 | leading bit is 0, so no XOR → 011 |
Remainder 011 ≠ 0 → error detected ✅.
9B.7 Why CRC detects errors
Let the sent frame be T(x) (divisible by G) and the error pattern be E(x). The receiver sees T(x) + E(x). The remainder is zero only if G(x) divides E(x). A well-chosen G rarely divides common error patterns, so the error is caught.
9B.8 What a good CRC detects
| Error type | Detected? |
|---|---|
| All single-bit errors | ✅ (if G has more than one term) |
| All odd-numbered bit errors | ✅ if G contains the factor (x + 1) |
| All burst errors up to r bits long | ✅ |
| Longer bursts | Detected with probability about 1 − 2⁻ʳ |
So a 32-bit CRC misses a random long error only about 1 time in 4 billion.
9B.9 Standard CRC generators
| Name | Bits (r) | Polynomial | Typical use |
|---|---|---|---|
| CRC-8 | 8 | x⁸ + x² + x + 1 | Small embedded links |
| CRC-16 (IBM) | 16 | x¹⁶ + x¹⁵ + x² + 1 | Storage, serial protocols |
| CRC-16-CCITT | 16 | x¹⁶ + x¹² + x⁵ + 1 | Communication protocols |
| CRC-32 | 32 | (IEEE 802.3 polynomial) | Ethernet, ZIP, PNG |
9B.10 Hardware idea
CRC is easy to build with a shift register and a few XOR gates (a linear-feedback shift register, LFSR). Bits are shifted in one at a time, so a CRC is computed on the fly as data streams past.
9C. Checksum vs CRC
| Feature | Checksum | CRC |
|---|---|---|
| Based on | Addition | Polynomial (XOR) division |
| Complexity | Very low | Low–moderate (cheap in hardware) |
| Detects burst errors | Weakly | Very well |
| Detects swapped/reordered data | ❌ Often not | ✅ Yes |
| Typical size | 8–16 bits | 8–32 bits |
| Typical use | Network headers, simple files | Ethernet frames, disks, ZIP/PNG files |
10. Applications of Coding in Digital Systems
10.1 Where each code shows up
| Code | Where it is used |
|---|---|
| BCD (8421) | Calculators, digital clocks, meters, and counters driving decimal displays (e.g. seven-segment) |
| 2421, 84-2-1, Excess-3 (self-complementing) | Decimal arithmetic units using 9's complement subtraction |
| Gray code | Shaft/position encoders, K-maps, low-power counters, clock-domain pointers, ADC outputs |
| ASCII / Unicode | Representing text in computers, keyboards, files, and communication |
| 2-out-of-5 and similar constant-weight codes | Simple self-checking decimal coding (e.g. some barcodes and legacy systems) |
| Parity bit | Serial links (UART), memory bytes, buses |
| 2-D parity | Tape and block storage with row and column checks |
| Hamming / SEC-DED codes | Computer memory (ECC RAM), caches, aerospace and server systems |
| Checksum | IP, TCP and UDP headers, simple file or firmware integrity checks |
| CRC | Ethernet, Wi-Fi frames, USB, hard disks and SSDs, ZIP and PNG files, embedded communication buses |
| Repetition codes | Very noisy or safety-critical signals (e.g. triple redundancy) |
10.2 Application areas
1. Data storage
- Memory chips and disks suffer random bit flips (from radiation, ageing or defects). ECC memory uses Hamming-type codes to correct single-bit errors and detect double-bit errors.
- Disk sectors and files carry CRCs to confirm that what is read equals what was written.
2. Data communication
- Every network frame ends with a CRC or checksum so the receiver can reject corrupted frames.
- Serial links use parity for quick per-character checking.
3. Position and motion sensing
- Gray-coded encoders give reliable angle or position readings in robots, machines, and instruments.
4. Decimal arithmetic and display
- BCD and Excess-3 let digital instruments compute and display decimal values exactly without converting entire numbers to binary.
5. Text and symbols
- ASCII and Unicode let every device agree on the bit pattern for each character.
6. Logic design
- Gray order on K-maps makes simplification of logic expressions possible.
10.3 Choosing a code: decision guide
| Need | Good choice |
|---|---|
| Show decimal digits exactly | BCD |
| Easy 9's complement subtraction | 2421 / Excess-3 |
| Avoid glitches when a value changes | Gray |
| Cheapest possible error detection | Parity bit |
| Detect and fix single-bit errors without retransmission | Hamming (SEC-DED) |
| Detect errors in blocks of data cheaply | Checksum |
| Strong protection against burst errors in frames or files | CRC |
| Represent text of any language | Unicode |
10.4 Common theme
All coding trades extra bits (cost) for reliability or convenience. Representation codes make information fit the hardware or the human; error-control codes make information survive the real, noisy world.
📝 Quick Revision Cheat Sheet
| Topic | Remember this |
|---|---|
| Weighted code | Value = sum of weights of the 1s (8421, 2421, 5421, 84-2-1) |
| Non-weighted code | No fixed weights (Excess-3, Gray, 2-out-of-5) |
| Self-complementing | Inverting all bits gives the 9's complement; weights must sum to 9 |
| Self-complementing codes | 2421, 84-2-1, 5211 (suitable assignment), Excess-3 |
| NOT self-complementing | 8421, 5421 |
| Gray code | One bit changes between consecutive words |
| Gray code uses | Encoders, K-maps, low-power counters, FIFO pointers, ADCs |
| Parity bit | One extra bit to make the number of 1s even or odd |
| Parity generator | XOR of data bits (even parity bit); complement for odd |
| Parity detects | Any odd number of bit errors; not even-numbered; cannot correct |
| Even vs odd parity | Total 1s even vs odd; odd parity catches an all-zero word |
| Hamming distance | Number of differing bit positions = weight of the XOR |
| Detect / correct | Detect d_min − 1; correct ⌊(d_min − 1)/2⌋ |
| Hamming code | d_min = 3; corrects 1 error |
| Check bits needed | 2ʳ ≥ m + r + 1 |
| Parity positions | Powers of 2 (1, 2, 4, 8, ...) |
| Syndrome | Failed check bits as a binary number = error position (000 = no error) |
| SEC-DED | Hamming + overall parity; corrects 1, detects 2; d_min = 4 |
| Detection | Notices errors; needs retransmission (ARQ) |
| Correction | Fixes errors; uses more redundancy (FEC) |
| Checksum | Sum of data bytes; send the complement; receiver sum gives 0 (2's) or all 1s (1's) |
| CRC | Mod-2 (XOR) division by a generator; send the remainder; receiver remainder 0 = OK |
| CRC strength | All bursts ≤ r bits; long errors missed about 2⁻ʳ of the time |
| Checksum vs CRC | CRC is much stronger, especially for bursts and reordering |
🧠 Practice Questions
- Classify each as weighted or non-weighted: 8421, Excess-3, 2421, Gray, 5421.
- Which of 8421, 2421, 5421 and Excess-3 are self-complementing? Explain the rule for weighted codes.
- Find the 9's complement of digit 4 in the 2421 code using bit inversion.
- Give two applications of Gray code and explain why Gray code is suitable for them.
- Add an even parity bit (as MSB) to the data
1100101. Repeat for odd parity. - Which of these 8-bit words (even parity) contain an error?
10110101,01100110. - Find the Hamming distance between
1011001and1101011. - A code has d_min = 5. How many errors can it detect? How many can it correct?
- How many check bits are needed to protect 12 data bits with a single-error-correcting Hamming code?
- Encode the data
1001with a (7,4) Hamming code (even parity). - A (7,4) Hamming word
0010001is received. Find the syndrome, the error position, and the corrected data. - Find the 8-bit 2's complement checksum of the bytes
12,A4,3F(hex). - Find the CRC for data
1010with generator1011, and write the transmitted frame. - Explain the difference between error detection and error correction, with one example technique for each.
- Why can a single parity bit not detect two-bit errors?
Click for answers
- Weighted: 8421, 2421, 5421. Non-weighted: Excess-3, Gray.
- Self-complementing: 2421 and Excess-3. 8421 (weights sum to 15) and 5421 (sum 12) are not. For weighted codes the weights must sum to 9.
- 4 =
0100→ invert →1011= 5 in 2421 → and 9 − 4 = 5 ✅. - Example answers: shaft/position encoders (only one bit changes at a boundary, so no wild misreads) and K-maps (adjacent cells differ in exactly one variable). Others: low-power counters, FIFO pointers across clock domains.
1100101has four 1s → even parity bit 0 →01100101. Odd parity bit 1 →11100101.10110101has five 1s (odd) → error.01100110has four 1s → no error detected.- XOR =
0110010→ three 1s → distance = 3. - Detects d_min − 1 = 4 errors; corrects ⌊4/2⌋ = 2 errors.
- r = 4 gives 16 ≥ 17? ❌. r = 5 gives 32 ≥ 18 ✅ → 5 check bits.
- D1 = 1, D2 = 0, D3 = 0, D4 = 1 at positions 3, 5, 6, 7. P1 (1,3,5,7): bits 1, 0, 1 → P1 = 0. P2 (2,3,6,7): 1, 0, 1 → P2 = 0. P4 (4,5,6,7): 0, 0, 1 → P4 = 1. Code word: 0011001.
- Received
0010001(positions 1 to 7 = 0,0,1,0,0,0,1). C1 (1,3,5,7) = 0,1,0,1 → 0. C2 (2,3,6,7) = 0,1,0,1 → 0. C4 (4,5,6,7) = 0,0,0,1 → 1. Syndrome100= position 4. Corrected word0011001; data (positions 3, 5, 6, 7) = 1001. - 12 + A4 = B6; B6 + 3F = F5. Checksum = 100 − F5 = 0B. Check: F5 + 0B = 100 → low 8 bits 00 ✅.
- Dividend
1010000÷1011:1010 ⊕ 1011 = 0001; bring down 0 →0010(no XOR); bring down 0 →0100(no XOR); bring down 0 →1000 ⊕ 1011 = 0011. CRC = 011; frame = 1010011. (Polynomial check: x⁶ + x⁴ mod (x³ + x + 1) = x + 1 =011✅.) - Detection only reveals that an error occurred (e.g. parity, checksum, CRC); the data must be resent. Correction finds and repairs the erroneous bits (e.g. Hamming code) and needs more redundancy.
- Two flipped bits change the count of 1s by an even amount (or leave it unchanged), so the parity of the word stays the same and the checker still sees a valid parity.
#Boolean Algebra and Logic Gates#
##Logic Gates#
Logic gates are the tiny decision-makers inside every digital device. Each one looks at one or more inputs (0 or 1) and decides what the output should be. Connect enough of them and you can build anything from a simple alarm to a full processor.
These notes go from the basics to the practical stuff, in the order below.
Table of Contents
- Before You Start: Binary Signals
- AND, OR and NOT Gates
- NAND and NOR Gates
- XOR and XNOR Gates
- Truth Tables and Boolean Expressions
- Universal Gates: NAND and NOR
- Implementing Functions Using Universal Gates
- Logic Gate Propagation Delay
- Fan-in and Fan-out
- Logic Levels and Noise Margins
- Practical Logic Gate ICs and Datasheets
- Quick Revision Cheat Sheet
0. Before You Start: Binary Signals
A digital circuit only cares about two states:
| Logic value | Meaning | Typical voltage (5 V system) |
|---|---|---|
| 1 (HIGH, True, ON) | signal is "present" | close to 5 V |
| 0 (LOW, False, OFF) | signal is "absent" | close to 0 V |
A logic gate is an electronic circuit that takes one or more such inputs and produces one output according to a fixed rule. The rule is described by a truth table (a list of every possible input combination and the resulting output) or a Boolean expression (an algebraic formula).
1. AND, OR and NOT Gates
These three are the basic gates. Every other gate can be built from them.
1.1 AND Gate
Idea: the output is 1 only when all inputs are 1.
Real-life picture: two switches in series with a bulb. The bulb glows only if switch A and switch B are both closed.
- Expression:
Y = A · B(also writtenABorA AND B)
| A | B | Y = A·B |
|---|---|---|
| 0 | 0 | 0 |
| 0 | 1 | 0 |
| 1 | 0 | 0 |
| 1 | 1 | 1 |
A ──┐
│ AND )──── Y
B ──┘
Handy facts:
- Any input of 0 forces the output to 0 (0 is the "controlling value").
- An input of 1 passes the other input through unchanged:
A · 1 = A. - An n-input AND has 2ⁿ rows in its truth table, and only the last row (all 1s) gives 1.
1.2 OR Gate
Idea: the output is 1 when at least one input is 1.
Real-life picture: two switches in parallel with a bulb. The bulb glows if A or B (or both) are closed.
- Expression:
Y = A + B(read "A or B", not "A plus B")
| A | B | Y = A+B |
|---|---|---|
| 0 | 0 | 0 |
| 0 | 1 | 1 |
| 1 | 0 | 1 |
| 1 | 1 | 1 |
A ──┐
│ OR )──── Y
B ──┘
Handy facts:
- Any input of 1 forces the output to 1 (1 is the controlling value).
- An input of 0 passes the other input through:
A + 0 = A.
1.3 NOT Gate (Inverter)
Idea: the output is the opposite of the input. It is the only basic gate with a single input.
- Expression:
Y = A'(also writtenĀor¬A)
| A | Y = A' |
|---|---|
| 0 | 1 |
| 1 | 0 |
A ──▷o── Y
The small circle (bubble) on the output means inversion. You will see this bubble on NAND, NOR and XNOR too.
Handy fact: two NOT gates in a row cancel out: (A')' = A. This is why a pair of inverters is sometimes used as a buffer, which passes the signal through but can drive a heavier load.
2. NAND and NOR Gates
These are the inverted versions of AND and OR. "N" stands for "NOT".
2.1 NAND Gate (NOT-AND)
Idea: it does exactly what AND does, then flips the result. The output is 0 only when all inputs are 1.
- Expression:
Y = (A · B)'
| A | B | A·B | Y = (A·B)' |
|---|---|---|---|
| 0 | 0 | 0 | 1 |
| 0 | 1 | 0 | 1 |
| 1 | 0 | 0 | 1 |
| 1 | 1 | 1 | 0 |
A ──┐
│ AND )o── Y
B ──┘
2.2 NOR Gate (NOT-OR)
Idea: it does what OR does, then flips the result. The output is 1 only when all inputs are 0.
- Expression:
Y = (A + B)'
| A | B | A+B | Y = (A+B)' |
|---|---|---|---|
| 0 | 0 | 0 | 1 |
| 0 | 1 | 1 | 0 |
| 1 | 0 | 1 | 0 |
| 1 | 1 | 1 | 0 |
A ──┐
│ OR )o── Y
B ──┘
2.3 Why do NAND and NOR matter?
- They are universal gates, so you can build any circuit from only one of them (see section 5).
- In CMOS technology, NAND and NOR are the simplest and fastest gates to build. AND and OR are actually made by adding an inverter to them.
2.4 De Morgan's Theorems (the link between AND/OR and NAND/NOR)
(A · B)' = A' + B' → NAND = OR of inverted inputs
(A + B)' = A' · B' → NOR = AND of inverted inputs
In words: "break the bar, change the sign." This gives each gate an alternate symbol:
| Gate | Standard symbol | Alternate (De Morgan) form |
|---|---|---|
| NAND | AND with output bubble | OR with bubbles on inputs |
| NOR | OR with output bubble | AND with bubbles on inputs |
3. XOR and XNOR Gates
3.1 XOR Gate (Exclusive OR)
Idea: the output is 1 when the inputs are different. Unlike OR, it gives 0 when both inputs are 1.
- Expression:
Y = A ⊕ B = A'B + AB'
| A | B | Y = A⊕B |
|---|---|---|
| 0 | 0 | 0 |
| 0 | 1 | 1 |
| 1 | 0 | 1 |
| 1 | 1 | 0 |
A ──┐
│ =1 )──── Y (XOR symbol: OR shape with an extra curved line)
B ──┘
Handy facts:
A ⊕ 0 = A(passes the signal through).A ⊕ 1 = A'(acts as a controllable inverter).A ⊕ A = 0andA ⊕ A' = 1.- For many inputs, XOR acts as an odd-parity detector: the output is 1 when an odd number of inputs are 1.
- It is the core of binary adders: the sum bit of a half adder is
A ⊕ B.
3.2 XNOR Gate (Exclusive NOR)
Idea: the output is 1 when the inputs are the same. It is the inversion of XOR, so it is also called the equivalence gate or coincidence gate.
- Expression:
Y = (A ⊕ B)' = A ⊙ B = AB + A'B'
| A | B | Y = A⊙B |
|---|---|---|
| 0 | 0 | 1 |
| 0 | 1 | 0 |
| 1 | 0 | 0 |
| 1 | 1 | 1 |
Handy facts:
- Used as a 1-bit comparator: output 1 means "A equals B".
- For many inputs, XNOR acts as an even-parity detector.
4. Truth Tables and Boolean Expressions
4.1 Truth Tables
A truth table lists every input combination and the output for each one.
Rules for building one:
- For n inputs, there are 2ⁿ rows (2 inputs → 4 rows, 3 inputs → 8 rows, 4 inputs → 16 rows).
- List the inputs in binary counting order (000, 001, 010, …) so you never miss or repeat a row.
- Fill in the output column by applying the gate or expression.
Example: Y = A·B + C (3 inputs, 8 rows)
| A | B | C | A·B | Y = A·B + C |
|---|---|---|---|---|
| 0 | 0 | 0 | 0 | 0 |
| 0 | 0 | 1 | 0 | 1 |
| 0 | 1 | 0 | 0 | 0 |
| 0 | 1 | 1 | 0 | 1 |
| 1 | 0 | 0 | 0 | 0 |
| 1 | 0 | 1 | 0 | 1 |
| 1 | 1 | 0 | 1 | 1 |
| 1 | 1 | 1 | 1 | 1 |
Tip: add helper columns (like A·B above) for intermediate results. It prevents mistakes in bigger expressions.
4.2 Boolean Expressions
A Boolean expression is an algebraic way of describing logic using three operators:
| Operator | Symbol | Meaning |
|---|---|---|
| AND | · or no symbol | both true |
| OR | + | at least one true |
| NOT | ' or overbar | opposite |
Precedence (highest to lowest): NOT → AND → OR. So A + B·C means A + (B·C).
4.3 Basic Boolean Laws
| Law | AND form | OR form |
|---|---|---|
| Identity | A · 1 = A | A + 0 = A |
| Null / Dominance | A · 0 = 0 | A + 1 = 1 |
| Idempotent | A · A = A | A + A = A |
| Complement | A · A' = 0 | A + A' = 1 |
| Double negation | (A')' = A | |
| Commutative | AB = BA | A + B = B + A |
| Associative | (AB)C = A(BC) | (A+B)+C = A+(B+C) |
| Distributive | A(B + C) = AB + AC | A + BC = (A+B)(A+C) |
| Absorption | A(A + B) = A | A + AB = A |
| De Morgan | (AB)' = A' + B' | (A+B)' = A'B' |
4.4 Standard Forms
Every Boolean function can be written in two standard ways.
Sum of Products (SOP): OR of AND terms, for example Y = AB + A'C.
- Built directly from the rows of the truth table where Y = 1.
- Each such row becomes a minterm (an AND of all variables, with a variable complemented if it is 0 in that row).
Product of Sums (POS): AND of OR terms, for example Y = (A + B)(A' + C).
- Built from the rows where Y = 0.
- Each such row becomes a maxterm (an OR of all variables, with a variable complemented if it is 1 in that row).
Example: a 2-input function that is 1 only for (A=0,B=1) and (A=1,B=0):
- SOP (minterms):
Y = A'B + AB'(which is exactly XOR) - Shorthand:
Y = Σm(1, 2)
4.5 From Expression to Circuit (and back)
- Expression → circuit: each operator becomes a gate. For
Y = A'B + C, you need one NOT, one AND and one OR. - Circuit → expression: work from the inputs to the output, writing the expression at each gate's output.
- Simplifying the expression with the laws above (or a Karnaugh map) reduces the number of gates needed, making the circuit cheaper and faster.
Simplification example:
Y = AB + AB'
= A(B + B') (distributive)
= A · 1 (complement)
= A (identity)
A whole AND-OR circuit collapses into a plain wire.
5. Universal Gates: NAND and NOR
A gate is called universal if you can build every other gate (AND, OR, NOT, and therefore any logic function) using only that gate. NAND and NOR are both universal. This is very useful in practice: a designer can stock a single type of gate IC and still build anything.
5.1 Building Basic Gates from NAND only
| Gate to make | How to build it with NAND |
|---|---|
| NOT | Tie both inputs together: (A·A)' = A' |
| AND | NAND followed by a NOT-made-from-NAND: ((A·B)')' = A·B |
| OR | Invert each input with a NAND-NOT, then NAND them: (A'·B')' = A + B |
| NOR | Build OR from NANDs, then add a NAND-NOT |
| XOR | 4 NAND gates (see below) |
NOT from NAND: AND from NAND: OR from NAND:
A ─┬─┐ A ─┐ A ──NAND(tied)─┐
│ NAND ─ A' NAND ─┬─ NAND(tied) ─ AB NAND ─ A+B
└─┘ B ─┘ └─┘ B ──NAND(tied)─┘
XOR using 4 NAND gates:
Let N1 = (A·B)'
N2 = (A·N1)'
N3 = (B·N1)'
Y = (N2·N3)' = A ⊕ B
5.2 Building Basic Gates from NOR only
| Gate to make | How to build it with NOR |
|---|---|
| NOT | Tie both inputs together: (A+A)' = A' |
| OR | NOR followed by a NOR-NOT: ((A+B)')' = A + B |
| AND | Invert each input with a NOR-NOT, then NOR them: (A'+B')' = A·B |
| NAND | Build AND from NORs, then add a NOR-NOT |
| XNOR | 4 NOR gates (mirror image of the NAND-XOR) |
5.3 Why do these work? (the De Morgan connection)
Both constructions rest on De Morgan's theorems:
A + B = (A' · B')'→ OR is "NAND of inverted inputs"A · B = (A' + B')'→ AND is "NOR of inverted inputs"
5.4 NAND vs NOR at a glance
| Feature | NAND | NOR |
|---|---|---|
| Universal? | Yes | Yes |
| Output is 1 when | any input is 0 | all inputs are 0 |
| Natural fit for | SOP (AND-OR) circuits | POS (OR-AND) circuits |
| Popularity (CMOS/TTL) | Generally preferred (faster, smaller for the same inputs) | Used less, slower with many inputs |
6. Implementing Functions Using Universal Gates
Here is the full method for turning any Boolean function into a circuit made of only NAND (or only NOR) gates.
6.1 Method A: SOP → Two-level NAND-NAND
A two-level AND-OR circuit can be replaced directly by a NAND-NAND circuit. This is the most commonly used trick.
Why it works: Y = AB + CD
Y = ((AB + CD)')'
= ((AB)' · (CD)')' (De Morgan)
- The first level
(AB)'and(CD)'is a layer of NAND gates. - The second level is a NAND gate that combines them.
Steps:
- Simplify the function into minimal SOP form.
- Draw the normal AND-OR circuit.
- Replace every AND and the OR with a NAND gate (bubbles cancel in pairs, so the logic stays identical).
- If a single literal goes straight into the second level (no AND gate), invert it first.
6.2 Method B: POS → Two-level NOR-NOR
The mirror image for product-of-sums:
Why it works: Y = (A + B)(C + D)
Y = ((A+B)' + (C+D)')' (De Morgan)
- The first level
(A+B)'and(C+D)'is a layer of NOR gates. - The second level is a NOR gate that combines them.
Steps:
- Simplify into minimal POS form.
- Draw the OR-AND circuit.
- Replace each OR and the AND with a NOR gate.
- If a single literal goes straight into the second level (no OR gate), invert it first (a NOR with tied inputs).
6.3 Bubble Pushing (a visual shortcut)
Using De Morgan's alternate symbols:
- Two bubbles on the same wire cancel each other.
- To convert, add a bubble on a gate's output and a bubble on the matching input of the next gate, since the net effect on the wire is zero.
6.4 Worked Example
Implement Y = AB + C'D using only NAND gates.
Step 1: Expression is already in SOP form.
Step 2: AND-OR form uses AND(A,B), AND(C',D), then OR.
Step 3: Convert to NAND-NAND.
N1 = (A·B)'
N2 = (C'·D)'
Y = (N1 · N2)' = AB + C'D
Step 4: C' needs an inverter, built as a NAND with tied inputs.
N3 = (C·C)' = C'
N2 = (N3·D)'
Total: 4 NAND gates (N3 for the inverter, N1, N2, and the output gate Y).
6.5 Worked Example: Half Adder with NAND only
A half adder has Sum = A ⊕ B and Carry = A · B.
N1 = (A·B)'
N2 = (A·N1)'
N3 = (B·N1)'
Sum = (N2·N3)' = A ⊕ B
Carry = (N1·N1)' = A·B (invert N1 with a NAND)
5 NAND gates build the whole half adder.
6.6 Tips
- Always simplify first. Fewer terms means fewer gates.
- Count gates and inputs: real cost depends on both.
- Convert XOR/XNOR into their AND-OR form before mapping to NAND or NOR.
- Check the final circuit by writing its expression and comparing with the original truth table.
7. Logic Gate Propagation Delay
7.1 What is it?
When an input changes, the output does not change instantly. There is a small delay because transistors take time to switch and wires and inputs have capacitance that must charge or discharge. This delay is the propagation delay, written tpd.
Input ____┌──────────────┐____
│ │
Output _______┌──────────────┐____
↑
t_pd
7.2 The two key numbers
| Symbol | Meaning |
|---|---|
| tPHL | delay for output going High → Low |
| tPLH | delay for output going Low → High |
Average propagation delay:
t_pd = (t_PHL + t_PLH) / 2
The delay is measured from the point where the input reaches 50% of its swing to the point where the output reaches 50% of its swing.
7.3 Related timing terms
- Rise time (tr): time for the output to go from 10% to 90% of its final value.
- Fall time (tf): time to go from 90% to 10%.
7.4 What affects it?
| Factor | Effect |
|---|---|
| Logic family (TTL, CMOS, etc.) | Different families have very different speeds |
| Supply voltage | Higher supply generally gives a faster CMOS gate |
| Load (what the gate drives) | More load capacitance and more connected inputs means a slower gate |
| Temperature | Delay usually grows as temperature rises |
| Gate complexity | Gates with more inputs are usually slower |
7.5 Why it matters
- Maximum speed: the clock frequency of a circuit is limited by the sum of delays along its slowest path (the critical path). If a signal goes through 5 gates of 10 ns each, the path delay is about 50 ns.
- Glitches / hazards: if two signal paths to the same gate have different delays, the output can briefly show a wrong value for a moment.
- Design trade-off: a faster gate usually uses more power. This is described by the speed-power product.
7.6 Example
Signal passes through: NAND (8 ns) → NOR (10 ns) → NOT (5 ns)
Total path delay = 8 + 10 + 5 = 23 ns
Max clock frequency ≈ 1 / 23 ns ≈ 43 MHz (ignoring other delays)
8. Fan-in and Fan-out
8.1 Fan-in
Fan-in = the number of inputs a gate has.
- A 2-input NAND has a fan-in of 2; an 8-input NAND has a fan-in of 8.
- Higher fan-in → the gate is slower and uses more silicon (especially in CMOS NOR gates with many series transistors).
- If you need a gate with more inputs than any IC provides, build it from a tree of smaller gates. For example, an 8-input AND can be made from 2-input ANDs arranged in 3 levels, which adds delay.
8.2 Fan-out
Fan-out = the maximum number of gate inputs that one gate output can drive reliably while still keeping its output in the valid logic-level range.
┌──── Gate 1 input
Gate output ──┼──── Gate 2 input ← this output has a fan-out load of 4
├──── Gate 3 input
└──── Gate 4 input
How to calculate it (current-based, mainly for TTL):
Fan-out (HIGH state) = I_OH(max) / I_IH
Fan-out (LOW state) = I_OL(max) / I_IL
Fan-out = the smaller of the two
| Symbol | Meaning |
|---|---|
| IOH | max current the output can source when HIGH |
| IOL | max current the output can sink when LOW |
| IIH | current an input draws when HIGH |
| IIL | current an input supplies when LOW |
Example (illustrative values): if a gate can sink 16 mA in LOW state and each input needs 1.6 mA, then LOW fan-out = 16 / 1.6 = 10.
8.3 CMOS vs TTL fan-out
- TTL: inputs draw real current, so fan-out is limited by current. Standard TTL has a fan-out of around 10.
- CMOS: inputs draw almost no DC current (they are like tiny capacitors), so the DC fan-out is very large. However, each input adds capacitance, which slows the output down. So the practical CMOS fan-out limit is set by speed (propagation delay), not by current.
8.4 What if the fan-out is exceeded?
- Output voltage levels drift out of the valid range, so a HIGH may no longer read as HIGH.
- Propagation delay increases.
- The gate heats up and may be damaged.
Fixes: use a buffer gate (made to drive heavy loads), split the load across several gates, or use a faster/stronger logic family.
9. Logic Levels and Noise Margins
9.1 Logic Levels
Real gates do not output exactly 0 V or 5 V, and they accept a range of voltages as 0 or 1. Datasheets define four voltage limits:
| Symbol | Name | Meaning |
|---|---|---|
| VIH(min) | Input HIGH voltage | lowest input voltage the gate is guaranteed to read as 1 |
| VIL(max) | Input LOW voltage | highest input voltage the gate is guaranteed to read as 0 |
| VOH(min) | Output HIGH voltage | lowest voltage the gate guarantees at its output for a 1 |
| VOL(max) | Output LOW voltage | highest voltage the gate guarantees at its output for a 0 |
5 V ┬─────────────────────
│ Output HIGH range (≥ V_OH)
│ - - - - - - - - - - V_OH(min)
│ ↕ NOISE MARGIN HIGH
│ - - - - - - - - - - V_IH(min)
│ FORBIDDEN / UNDEFINED region
│ - - - - - - - - - - V_IL(max)
│ ↕ NOISE MARGIN LOW
│ - - - - - - - - - - V_OL(max)
│ Output LOW range (≤ V_OL)
0 V ┴─────────────────────
The forbidden (undefined) region lies between VIL(max) and VIH(min). A signal sitting here may be read as 0 or 1 unpredictably, so circuits must pass through it quickly and never stay there.
9.2 Noise Margin
Noise margin is how much unwanted voltage (noise) a signal can pick up on the wire and still be read correctly.
The driving gate's output is always "better" than what the receiving gate requires. The gap is the safety margin:
Noise Margin HIGH: NM_H = V_OH(min) − V_IH(min)
Noise Margin LOW: NM_L = V_IL(max) − V_OL(max)
The overall noise margin of a circuit is the smaller of NMH and NML.
9.3 Example with typical TTL values
| Parameter | Value |
|---|---|
| VOH(min) | 2.4 V |
| VIH(min) | 2.0 V |
| VIL(max) | 0.8 V |
| VOL(max) | 0.4 V |
NM_H = 2.4 − 2.0 = 0.4 V
NM_L = 0.8 − 0.4 = 0.4 V
So a standard TTL signal can tolerate roughly 0.4 V of noise in either state.
9.4 Comparison of families (typical, approximate)
| Feature | TTL (74LS, 5 V) | CMOS (74HC, 5 V) |
|---|---|---|
| Supply voltage | 5 V (4.75–5.25 V) | 2 V to 6 V |
| VIH(min) | 2.0 V | ~3.5 V |
| VIL(max) | 0.8 V | ~1.5 V |
| Output swing | not quite rail-to-rail | almost rail-to-rail (0 V to VCC) |
| Noise margin | ~0.4 V | much better (~30% of VCC) |
| Static power | higher | very low |
Always read the exact numbers from the datasheet of the part you are using.
9.5 Mixing Families
When one family drives another (for example TTL output to CMOS input), check that the driver's VOH(min) is greater than the receiver's VIH(min), and the driver's VOL(max) is less than the receiver's VIL(max). A TTL output (VOH 2.4 V) may not be high enough for a standard 5 V CMOS input (needs ~3.5 V). That is why the HCT family exists: CMOS technology with TTL-compatible input levels.
9.6 Unused Inputs
Never leave an input floating (unconnected). A floating input picks up noise and can sit in the forbidden region. Tie unused inputs to:
- VCC (for AND/NAND gates, so they don't affect the logic), or
- GND (for OR/NOR gates), or
- connect them to another used input of the same gate.
This matters most for CMOS, where floating inputs can cause erratic output and wasted current.
10. Practical Logic Gate ICs and Datasheets
10.1 What is a logic gate IC?
Gates come packaged in integrated circuits. A single chip normally holds several identical gates. The classic package is the 14-pin DIP (Dual In-line Package), with the notch (or dot) marking pin 1.
┌───╮ ╭───┐
Pin 1 │ 1 ╰─╯ 14│ Pin 14 = V_CC (+5 V)
│ 2 13│
│ 3 12│
│ 4 11│
│ 5 10│
│ 6 9│
Pin 7 = │ 7 8│
GND └─────────┘
Pins are counted anticlockwise starting from the notch. On most 14-pin gate ICs, pin 14 is VCC and pin 7 is GND.
10.2 Common 74-series gate ICs
| IC number | What's inside |
|---|---|
| 7400 | Quad 2-input NAND |
| 7402 | Quad 2-input NOR |
| 7404 | Hex NOT (inverter) |
| 7408 | Quad 2-input AND |
| 7432 | Quad 2-input OR |
| 7486 | Quad 2-input XOR |
| 7410 | Triple 3-input NAND |
| 7420 | Dual 4-input NAND |
| 7411 | Triple 3-input AND |
| 7427 | Triple 3-input NOR |
"Quad" = 4 gates, "Hex" = 6, "Triple" = 3, "Dual" = 2.
Pinout warning: most 2-input gate ICs (7400, 7408, 7432, 7486) share a pinout where inputs are pins 1, 2 → output pin 3, and so on. The 7402 NOR is different: its output is on pins 1, 4, 10, 13. Always check the datasheet!
7400 pin arrangement (quad NAND):
Pin: 1 2 3 4 5 6 7
1A 1B 1Y 2A 2B 2Y GND
Pin: 8 9 10 11 12 13 14
3Y 3B 3A 4Y 4B 4A VCC
10.3 Reading the part number
Example: SN74HC00N
| Part | Meaning |
|---|---|
SN | manufacturer prefix (Texas Instruments) |
74 | commercial temperature range, standard 74-series (the 54 series is the military range) |
HC | logic family (High-speed CMOS) |
00 | function (quad 2-input NAND) |
N | package type (plastic DIP) |
10.4 Common logic families
| Family | Meaning | Notes |
|---|---|---|
| 74 / 74LS | Standard TTL / Low-power Schottky TTL | Older; 5 V only |
| 74HC | High-speed CMOS | Low power, wide supply range, CMOS levels |
| 74HCT | High-speed CMOS, TTL-compatible inputs | Easy interface with TTL |
| 74AHC / 74LVC | Advanced / Low-voltage CMOS | Faster, work at 3.3 V and lower |
| 4000-series (e.g. CD4011) | Older CMOS | Wide supply (3–15 V), slow |
10.5 Special output types you will meet
- Open-collector / open-drain (e.g. 7401, 7403): the output can only pull LOW; a pull-up resistor is needed to get a HIGH. Several outputs can be wired together (wired-AND).
- Schmitt-trigger inputs (e.g. 7414): the input has two different thresholds (hysteresis), which cleans up slow or noisy signals.
- Totem-pole outputs: the standard output stage that actively drives both HIGH and LOW. Never connect two totem-pole outputs together.
- Tri-state outputs: can be HIGH, LOW, or disconnected (high-impedance).
10.6 How to read a datasheet
A datasheet is the manufacturer's official specification. Learn where to look:
| Section | What you find there |
|---|---|
| Description / Features | Function, family, number of gates, supply range |
| Pin configuration / Pinout | Which pin does what (top view) |
| Function table (truth table) | Logic of the gate |
| Absolute maximum ratings | Limits that must never be exceeded (supply voltage, input voltage, temperature). Going past these can destroy the chip |
| Recommended operating conditions | Safe range for normal use (VCC, temperature, input voltage) |
| Electrical characteristics (DC) | VIH, VIL, VOH, VOL, IIH, IIL, IOH, IOL, supply current |
| Switching characteristics (AC) | tPLH, tPHL (propagation delay), rise and fall times |
| Package information | Physical dimensions and package types |
Key tip: the datasheet gives values at specific conditions (for example, "at VCC = 4.5 V, CL = 50 pF"). Always check that your conditions match, and design using min/max values rather than just typical ones.
10.7 Practical tips for using gate ICs
- Power it correctly: connect VCC and GND before anything else, and keep within the recommended voltage.
- Add a decoupling capacitor (about 0.1 µF) between VCC and GND, close to the chip, to absorb switching spikes.
- Tie off unused inputs (see section 9.6), and leave unused outputs unconnected.
- Respect fan-out limits when one output drives several inputs.
- Handle CMOS carefully: it is sensitive to static electricity (ESD), so avoid touching the pins directly.
- Check pin 1 orientation before powering up. A reversed chip can be damaged.
Quick Revision Cheat Sheet
All gates in one table
| Gate | Expression | Output is 1 when… |
|---|---|---|
| NOT | A' | input is 0 |
| AND | A·B | all inputs are 1 |
| OR | A+B | at least one input is 1 |
| NAND | (A·B)' | at least one input is 0 |
| NOR | (A+B)' | all inputs are 0 |
| XOR | A⊕B | inputs are different |
| XNOR | (A⊕B)' | inputs are the same |
Truth table summary (2 inputs)
| A | B | AND | OR | NAND | NOR | XOR | XNOR |
|---|---|---|---|---|---|---|---|
| 0 | 0 | 0 | 0 | 1 | 1 | 0 | 1 |
| 0 | 1 | 0 | 1 | 1 | 0 | 1 | 0 |
| 1 | 0 | 0 | 1 | 1 | 0 | 1 | 0 |
| 1 | 1 | 1 | 1 | 0 | 0 | 0 | 1 |
Formulas to remember
De Morgan: (AB)' = A' + B' (A+B)' = A'B'
Avg prop delay: t_pd = (t_PHL + t_PLH) / 2
Fan-out: min( I_OH / I_IH , I_OL / I_IL )
Noise margins: NM_H = V_OH(min) − V_IH(min)
NM_L = V_IL(max) − V_OL(max)
Common mistakes to avoid
- Reading
+in Boolean algebra as arithmetic addition (1 + 1 = 1, not 2). - Forgetting that XOR gives 0 when both inputs are 1 (OR gives 1).
- Leaving CMOS inputs floating.
- Assuming all 14-pin gate ICs share the same pinout (the 7402 is different).
- Using typical datasheet values instead of worst-case min/max values.
- Connecting two ordinary (totem-pole) outputs together.
One-line summary of each topic
| Topic | In one line |
|---|---|
| AND, OR, NOT | The three building blocks of all digital logic |
| NAND, NOR | AND/OR followed by inversion |
| XOR, XNOR | Detect "different" and "same" |
| Truth tables / Boolean expressions | Two ways of describing exactly the same logic |
| Universal gates | NAND alone or NOR alone can build everything |
| Implementing with universal gates | SOP → NAND-NAND, POS → NOR-NOR |
| Propagation delay | The time a gate takes to respond |
| Fan-in / Fan-out | Inputs a gate has / loads a gate can drive |
| Logic levels / noise margins | Valid voltage ranges and the safety gap against noise |
| ICs and datasheets | Real chips, their pinouts, and how to read their specs |
##Boolean Algebra#
Boolean algebra is the "mathematics of 0s and 1s". It gives you a set of rules for writing, simplifying and transforming logic expressions, so that a messy circuit idea can be turned into a clean, minimal one.
These notes follow the topic list in order, from the basic vocabulary up to canonical forms and complementation.
Table of Contents
- Boolean Variables, Operators and Expressions
- Fundamental Boolean Laws (Overview)
- Identity, Null, Idempotent and Complement Laws
- Commutative, Associative and Distributive Laws
- Absorption and Involution Laws
- De Morgan's Theorems
- Duality Principle
- Simplification of Boolean Expressions
- SOP (Sum of Products)
- POS (Product of Sums)
- Minterms and Maxterms
- Canonical SOP and POS
- Truth-Table-to-Expression Conversion
- Complementation of Boolean Functions
- Quick Revision Cheat Sheet
1. Boolean Variables, Operators and Expressions
1.1 Boolean variables and constants
- A Boolean variable is a symbol (like
A,B,X) that can hold only one of two values:0or1. - The two constants are
0(false / LOW) and1(true / HIGH). - The complement of a variable is written
A'(or Ā). IfA = 1thenA' = 0, and vice versa. - A literal is a variable in either form:
AandA'are two different literals of the same variable.
1.2 The three basic operators
| Operator | Symbol(s) | Read as | Result |
|---|---|---|---|
| NOT (complement) | A' or Ā | "not A" | flips the value |
| AND (product) | A · B or AB | "A and B" | 1 only if both are 1 |
| OR (sum) | A + B | "A or B" | 1 if at least one is 1 |
| A | B | A' | A·B | A+B |
|---|---|---|---|---|
| 0 | 0 | 1 | 0 | 0 |
| 0 | 1 | 1 | 0 | 1 |
| 1 | 0 | 0 | 0 | 1 |
| 1 | 1 | 0 | 1 | 1 |
Important: the
+here means OR, not arithmetic addition. So1 + 1 = 1in Boolean algebra. Likewise·means AND, so it behaves like multiplication of 0s and 1s.
1.3 Precedence (order of evaluation)
- Parentheses
( )first - NOT (
') - AND (
·) - OR (
+)
So A + B·C' means A + (B·(C')). When in doubt, add brackets.
1.4 Boolean expressions and functions
A Boolean expression combines variables, constants and operators, for example:
F = A·B' + C
A Boolean function assigns an output (0 or 1) to every combination of its inputs. The same function can be written as many different (but equivalent) expressions; simplification is about finding the shortest one.
Evaluating an expression: substitute the values and apply the precedence rules.
F = A·B' + C with A = 1, B = 0, C = 0
= 1·(0)' + 0
= 1·1 + 0
= 1 + 0
= 1
1.5 Useful vocabulary
| Term | Meaning | Example |
|---|---|---|
| Product term | literals joined by AND | AB'C |
| Sum term | literals joined by OR | A + B' + C |
| Equivalent expressions | give the same output for every input combination | A + AB and A |
For n variables there are 2ⁿ possible input combinations (rows in a truth table).
2. Fundamental Boolean Laws (Overview)
Boolean algebra is built on a small set of laws. Every law below can be proven by a truth table (try all input combinations and check both sides match).
| Law | AND form | OR form |
|---|---|---|
| Identity | A · 1 = A | A + 0 = A |
| Null (Dominance) | A · 0 = 0 | A + 1 = 1 |
| Idempotent | A · A = A | A + A = A |
| Complement | A · A' = 0 | A + A' = 1 |
| Involution | (A')' = A | |
| Commutative | AB = BA | A + B = B + A |
| Associative | (AB)C = A(BC) | (A+B)+C = A+(B+C) |
| Distributive | A(B+C) = AB + AC | A + BC = (A+B)(A+C) |
| Absorption | A(A+B) = A | A + AB = A |
| De Morgan | (AB)' = A' + B' | (A+B)' = A'B' |
Notice that almost every law appears twice, once in an AND form and once in an OR form. That symmetry is the duality principle (section 7).
3. Identity, Null, Idempotent and Complement Laws
3.1 Identity law
Combining a variable with the "neutral" constant leaves it unchanged.
A · 1 = A (ANDing with 1 changes nothing)
A + 0 = A (ORing with 0 changes nothing)
- If
A = 1:1·1 = 1✓ IfA = 0:0·1 = 0✓
3.2 Null law (also called Dominance or Annulment)
Combining a variable with the "overpowering" constant forces the result.
A · 0 = 0 (anything ANDed with 0 is 0)
A + 1 = 1 (anything ORed with 1 is 1)
Think of it as: a single 0 kills an AND, and a single 1 wins an OR.
3.3 Idempotent law
Repeating the same variable has no effect.
A · A = A
A + A = A
Generalised: A·A·A·...·A = A and A+A+...+A = A. This lets you add or remove duplicate terms freely.
3.4 Complement law
A variable and its opposite always cancel in a predictable way.
A · A' = 0 (A and not-A can never both be true)
A + A' = 1 (either A or not-A is always true)
3.5 Quick example using all four
Y = (A + 0)(A + A)(A' + 1)
Simplify step by step:
(A + 0) = A (identity)
(A + A) = A (idempotent)
(A' + 1) = 1 (null)
Y = A · A · 1 = A · A = A (identity, idempotent)
4. Commutative, Associative and Distributive Laws
4.1 Commutative law (order does not matter)
A + B = B + A
A · B = B · A
Swapping inputs of an AND or OR gate does not change the output.
4.2 Associative law (grouping does not matter)
(A + B) + C = A + (B + C) = A + B + C
(A · B) · C = A · (B · C) = A · B · C
This is why a 3-input OR gate can be built from two 2-input OR gates in either grouping.
4.3 Distributive law
Two forms, and the second one has no counterpart in ordinary algebra:
Form 1 (AND over OR): A · (B + C) = A·B + A·C
Form 2 (OR over AND): A + (B · C) = (A + B) · (A + C)
Proof of Form 2 (using the other laws):
(A + B)(A + C) = AA + AC + AB + BC
= A + AC + AB + BC (idempotent: AA = A)
= A(1 + C + B) + BC (factor out A)
= A·1 + BC (null: 1 + anything = 1)
= A + BC ✓
Where each form is used:
- Form 1 is used to multiply out a product into a sum, giving SOP form.
- Form 2 is used to factor a sum into a product, giving POS form.
Example of Form 2 for converting to POS:
A + B·C = (A + B)(A + C)
5. Absorption and Involution Laws
5.1 Absorption law
A larger term gets "absorbed" by a smaller term that is contained inside it.
A + A·B = A
A · (A + B) = A
Proofs:
A + AB = A(1 + B) = A · 1 = A
A(A + B) = AA + AB = A + AB = A (using the first result)
Plain-language meaning: in A + AB, if A is 1 the output is already 1, so AB adds nothing. If A is 0 then AB is 0 anyway. Either way the output equals A.
A closely related and very useful result:
A + A'B = A + B
A · (A' + B) = A · B
Proof of the first:
A + A'B = (A + A')(A + B) (distributive, Form 2)
= 1 · (A + B) (complement)
= A + B ✓
This one removes a complemented variable from a term, and you will use it constantly during simplification.
5.2 Involution law (double negation)
Complementing twice brings you back to the start.
(A')' = A
Also written as Ā with a double bar: A with two bars equals A. So ((A+B)')' = A + B.
6. De Morgan's Theorems
These two theorems tell you how to complement an AND or an OR. They are the bridge between sums and products.
6.1 The theorems
Theorem 1: (A · B)' = A' + B' "NAND = OR of the complements"
Theorem 2: (A + B)' = A' · B' "NOR = AND of the complements"
Memory trick: "Break the line, change the sign." Break the bar over the expression, switch AND ↔ OR, and complement each part.
6.2 Proof of Theorem 1 by truth table
| A | B | A·B | (A·B)' | A' | B' | A'+B' |
|---|---|---|---|---|---|---|
| 0 | 0 | 0 | 1 | 1 | 1 | 1 |
| 0 | 1 | 0 | 1 | 1 | 0 | 1 |
| 1 | 0 | 0 | 1 | 0 | 1 | 1 |
| 1 | 1 | 1 | 0 | 0 | 0 | 0 |
The bold columns match in every row, so the theorem holds. Theorem 2 is proven the same way.
6.3 Extension to any number of variables
(A · B · C · ... · N)' = A' + B' + C' + ... + N'
(A + B + C + ... + N)' = A' · B' · C' · ... · N'
6.4 Applying De Morgan to bigger expressions
Work from the outside in, one bar at a time.
Example 1: (AB + CD)'
(AB + CD)' = (AB)' · (CD)' (Theorem 2: treat AB and CD as single terms)
= (A' + B') · (C' + D') (Theorem 1 on each part)
Example 2: (A' + B·C)'
(A' + BC)' = (A')' · (BC)' (Theorem 2)
= A · (B' + C') (involution, then Theorem 1)
Example 3: ((A + B)' · C)'
= ((A + B)')' + C' (Theorem 1)
= (A + B) + C' (involution)
= A + B + C'
7. Duality Principle
7.1 Statement
Every Boolean law stays true if you swap all AND ↔ OR and all 0 ↔ 1.
The expression you get after the swap is called the dual.
7.2 How to write the dual
- Replace every
+with·and every·with+. - Replace every
0with1and every1with0. - Do not complement the variables. Keep them as they are.
- Keep the original evaluation order (add brackets where needed, since AND normally beats OR).
7.3 Examples
| Original | Dual |
|---|---|
A + 0 = A | A · 1 = A |
A + 1 = 1 | A · 0 = 0 |
A + A' = 1 | A · A' = 0 |
A + AB = A | A · (A + B) = A |
A + BC = (A+B)(A+C) | A · (B + C) = AB + AC |
(AB)' = A' + B' | (A + B)' = A'B' |
Example with a function:
F = A · (B + C')
Dual = A + (B · C')
7.4 Why it is useful
- You only need to prove one law; its dual is automatically true. That halves the work of learning the laws.
- This is why the laws come in pairs.
7.5 Dual vs complement: do not confuse them!
| Dual | Complement | |
|---|---|---|
| Swap AND/OR and 0/1 | Yes | Yes (the result is equivalent) |
| Complement the variables | No | Yes |
| Is it equal to the original function? | Generally no | It is the opposite function |
F = A + B'
Dual of F = A · B'
Complement of F = F' = A' · B (De Morgan)
A handy relationship: the complement of F equals its dual with every literal complemented. Here the dual is A·B'; complementing the literals gives A'·B = F' ✓.
8. Simplification of Boolean Expressions
8.1 Why simplify?
A simpler expression means fewer gates, fewer connections, less cost, lower delay and less power, while giving exactly the same output.
8.2 General strategy
- Multiply out brackets (distributive law) to get a sum of products.
- Look for common factors and take them out:
AB + AC = A(B + C). - Apply idempotent, complement, identity and null laws to remove or merge terms.
- Use absorption:
A + AB = AandA + A'B = A + B. - Use De Morgan to remove long bars over several variables.
- Check the result with a truth table if you are unsure.
8.3 Key patterns to recognise
| Pattern | Simplifies to |
|---|---|
AB + AB' | A |
(A + B)(A + B') | A |
A + AB | A |
A + A'B | A + B |
A(A' + B) | AB |
(A + B)(A + C) | A + BC |
AB + A'C + BC | AB + A'C |
8.4 Worked examples
Example 1: Y = AB + AB' + A'B
Y = A(B + B') + A'B (factor A from the first two terms)
= A · 1 + A'B (complement)
= A + A'B (identity)
= A + B (A + A'B = A + B)
Example 2: Y = A'B'C + A'BC + AB'C + ABC
Y = C(A'B' + A'B + AB' + AB) (factor C)
= C(A'(B' + B) + A(B' + B)) (group by A', A)
= C(A' · 1 + A · 1) (complement)
= C(A' + A)
= C · 1 = C
Four AND gates and an OR gate collapse into just the signal C.
Example 3: Y = (A + B)(A + C)
Y = A + BC (distributive law, Form 2)
Example 4: Y = A·B + A·B·C + A'·B
Y = AB(1 + C) + A'B (factor AB from the first two)
= AB · 1 + A'B (null law)
= AB + A'B
= B(A + A') = B (factor B, complement)
Example 5 (the "consensus" trick): Y = AB + A'C + BC
Y = AB + A'C + BC(A + A') (multiply BC by 1 = A + A')
= AB + A'C + ABC + A'BC
= AB(1 + C) + A'C(1 + B) (group)
= AB + A'C (null law)
The term BC was redundant, so it disappears.
Example 6 (using De Morgan first): Y = (A + B)' + A'B'
Y = (A + B)' + A'B'
= A'B' + A'B' (De Morgan on the first term)
= A'B' (idempotent)
8.5 Tips
- Do one law at a time, and write which law you are using.
- Introducing
A + A'(= 1) orA·1can help expand a term, but only do this when it leads to a simplification. - There may be more than one correct minimal answer. What matters is that it is equivalent and has no obvious redundancy.
9. SOP (Sum of Products)
9.1 Definition
An expression is in Sum of Products (SOP) form when it is an OR of AND terms.
F = AB + A'C + BC'
↑ ↑ ↑
product terms ORed together
- Each AND term is a product term.
- Each product term can have one or more literals.
- The AND terms are joined by
+.
9.2 Examples
| Expression | Is it SOP? |
|---|---|
AB + CD | Yes |
A + BC' | Yes (a single literal counts as a product term) |
A'B'C + AB' | Yes |
(A + B)C | No (a sum is inside a product) |
(AB + C)' | No (a bar over a group) |
9.3 How to get SOP form
- Multiply out any brackets using the distributive law.
- Remove big bars using De Morgan so that bars sit only over single variables.
F = (A + B)(C + D)
= AC + AD + BC + BD ← SOP
9.4 Circuit view
SOP maps naturally onto a two-level AND-OR circuit: a layer of AND gates (one per product term) feeding one OR gate.
9.5 Standard vs canonical SOP
- Non-canonical (standard) SOP: product terms may be missing some variables, e.g.
AB + C. - Canonical SOP: every product term contains all the variables (see section 12).
10. POS (Product of Sums)
10.1 Definition
An expression is in Product of Sums (POS) form when it is an AND of OR terms.
F = (A + B)(A' + C)(B + C')
↑ ↑ ↑
sum terms ANDed together
10.2 Examples
| Expression | Is it POS? |
|---|---|
(A + B)(C + D) | Yes |
A(B' + C) | Yes (a single literal counts as a sum term) |
(A + B' + C)(A' + C) | Yes |
AB + C | No |
((A + B)C)' | No (a bar over a group) |
10.3 How to get POS form
Use the second distributive law, A + BC = (A + B)(A + C), to factor sums out of products.
F = AB + CD
= (AB + C)(AB + D)
= (A + C)(B + C)(A + D)(B + D) ← POS
10.4 Circuit view
POS maps onto a two-level OR-AND circuit: a layer of OR gates feeding one AND gate.
10.5 SOP and POS side by side
| SOP | POS | |
|---|---|---|
| Structure | AND terms ORed | OR terms ANDed |
| Built from truth-table rows where | F = 1 | F = 0 |
| Canonical building blocks | Minterms | Maxterms |
| Two-level circuit | AND-OR | OR-AND |
Both forms describe the same function; pick whichever is shorter or easier for your circuit.
11. Minterms and Maxterms
These are the "building blocks" of canonical forms. Both use all variables exactly once.
11.1 Minterm
A minterm is an AND (product) of all variables, each appearing once, either complemented or not. It equals 1 for exactly one input combination and 0 for all others.
Rule: for row number i, write the variable as is if its bit is 1, and complemented if its bit is 0.
Example for row A=1, B=0, C=1 (binary 101 = row 5): m₅ = A · B' · C.
11.2 Maxterm
A maxterm is an OR (sum) of all variables, each appearing once, either complemented or not. It equals 0 for exactly one input combination and 1 for all others.
Rule (opposite to minterms): for row i, write the variable complemented if its bit is 1, and as is if its bit is 0.
Example for row 101 (row 5): M₅ = A' + B + C'.
11.3 Full table for 3 variables
| Row | A B C | Minterm (mᵢ) | Maxterm (Mᵢ) |
|---|---|---|---|
| 0 | 0 0 0 | A'B'C' | A + B + C |
| 1 | 0 0 1 | A'B'C | A + B + C' |
| 2 | 0 1 0 | A'BC' | A + B' + C |
| 3 | 0 1 1 | A'BC | A + B' + C' |
| 4 | 1 0 0 | AB'C' | A' + B + C |
| 5 | 1 0 1 | AB'C | A' + B + C' |
| 6 | 1 1 0 | ABC' | A' + B' + C |
| 7 | 1 1 1 | ABC | A' + B' + C' |
11.4 Key relationship
A maxterm is the complement of the minterm with the same number, and vice versa:
Mᵢ = (mᵢ)' and mᵢ = (Mᵢ)'
Check with row 5: (m₅)' = (AB'C)' = A' + B + C' = M₅ ✓ (by De Morgan).
11.5 Quick facts
| Fact | Detail |
|---|---|
| Number of minterms for n variables | 2ⁿ |
| Number of maxterms for n variables | 2ⁿ |
| A minterm is 1 when | the row matches its own number only |
| A maxterm is 0 when | the row matches its own number only |
| Notation | mᵢ (small m), Mᵢ (capital M) |
12. Canonical SOP and POS
A canonical form is a standard, unique way of writing a function, where every term contains all the variables.
12.1 Canonical SOP (sum of minterms)
The function is written as the OR of the minterms for which F = 1.
F(A,B,C) = m₁ + m₄ + m₆ = Σm(1, 4, 6)
The symbol Σ means "sum (OR) of minterms", and the numbers are the row numbers where F is 1.
12.2 Canonical POS (product of maxterms)
The function is written as the AND of the maxterms for which F = 0.
F(A,B,C) = M₀ · M₂ · M₃ = Π M(0, 2, 3)
The symbol Π means "product (AND) of maxterms", and the numbers are the row numbers where F is 0.
12.3 The two forms describe the same function
For an n-variable function with 2ⁿ rows:
- Rows where F = 1 → listed in Σm
- Rows where F = 0 → listed in ΠM
- Together they cover every row exactly once.
So Σm(1, 4, 5, 6, 7) = ΠM(0, 2, 3) for 3 variables (the rows 0–7 are split between the two lists).
12.4 Converting a non-canonical SOP to canonical SOP
Method: for every product term that is missing a variable, AND it with (X + X') (which equals 1) for each missing variable X, then expand and remove duplicates.
Example: F = A + B'C (3 variables A, B, C)
A = A(B + B')(C + C')
= ABC + ABC' + AB'C + AB'C'
B'C = B'C(A + A')
= AB'C + A'B'C
F = ABC + ABC' + AB'C + AB'C' + AB'C + A'B'C
= ABC + ABC' + AB'C + AB'C' + A'B'C (idempotent: remove the duplicate AB'C)
= m₇ + m₆ + m₅ + m₄ + m₁
= Σm(1, 4, 5, 6, 7)
12.5 Converting a non-canonical POS to canonical POS
Method: for every sum term that is missing a variable, OR it with (X · X') (which equals 0) for each missing variable X, then use the distributive law A + BC = (A+B)(A+C) to split it and remove duplicates.
Example: F = (A + B)(A' + C) (3 variables)
A + B = A + B + CC' = (A + B + C)(A + B + C')
A' + C = A' + C + BB' = (A' + B + C)(A' + B' + C)
F = (A+B+C)(A+B+C')(A'+B+C)(A'+B'+C)
= M₀ · M₁ · M₄ · M₆
= Π M(0, 1, 4, 6)
12.6 Converting between Σm and ΠM
Take the row numbers that are missing from the list.
F = Σm(1, 4, 6) → F = ΠM(0, 2, 3, 5, 7) (3 variables: rows 0 to 7)
F = ΠM(0, 2, 3) → F = Σm(1, 4, 5, 6, 7)
12.7 Canonical vs minimal
- Canonical forms are unique and complete, but usually longer than needed.
- Simplification (section 8) reduces them to a minimal form.
- A function with 3 variables has 2³ = 8 rows, so at most 8 terms in its canonical form.
13. Truth-Table-to-Expression Conversion
This is how you turn a "what should the circuit do?" table into an expression.
13.1 Method 1: SOP (use the rows where F = 1)
- Mark every row where the output is 1.
- For each such row, write a minterm (variable as is if its bit is 1, complemented if 0).
- OR all the minterms together.
- Simplify if you can.
13.2 Method 2: POS (use the rows where F = 0)
- Mark every row where the output is 0.
- For each such row, write a maxterm (variable complemented if its bit is 1, as is if 0).
- AND all the maxterms together.
- Simplify if you can.
Which to pick? Use SOP if there are fewer 1s than 0s, and POS if there are fewer 0s than 1s. You will write fewer terms.
13.3 Worked example
| Row | A | B | C | F |
|---|---|---|---|---|
| 0 | 0 | 0 | 0 | 0 |
| 1 | 0 | 0 | 1 | 1 |
| 2 | 0 | 1 | 0 | 0 |
| 3 | 0 | 1 | 1 | 0 |
| 4 | 1 | 0 | 0 | 1 |
| 5 | 1 | 0 | 1 | 0 |
| 6 | 1 | 1 | 0 | 1 |
| 7 | 1 | 1 | 1 | 1 |
SOP (rows 1, 4, 6, 7):
F = A'B'C + AB'C' + ABC' + ABC
= Σm(1, 4, 6, 7)
POS (rows 0, 2, 3, 5):
F = (A + B + C)(A + B' + C)(A + B' + C')(A' + B + C')
= Π M(0, 2, 3, 5)
Simplifying the SOP:
AB'C' + ABC' = AC'(B' + B) = AC'
ABC' + ABC = AB(C' + C) = AB (ABC' can be reused thanks to the idempotent law)
F = A'B'C + AC' + AB
Both the canonical SOP and the canonical POS, and this simplified expression, all give the same truth table.
13.4 Going the other way (expression → truth table)
- List all 2ⁿ input combinations in binary counting order.
- Evaluate the expression for each row (use helper columns for sub-terms).
- Write down the outputs.
14. Complementation of Boolean Functions
The complement F' of a function is 1 exactly where F is 0, and 0 exactly where F is 1. There are three standard ways to find it.
14.1 Method 1: Apply De Morgan's theorems
Complement the whole expression, then push the bars inward, switching AND ↔ OR and complementing each literal.
Example: F = A'B'C + AB + AC'
F' = (A'B'C)' · (AB)' · (AC')'
= (A + B + C') · (A' + B') · (A' + C)
14.2 Method 2: Dual, then complement each literal
- Write the dual of F (swap AND ↔ OR, 0 ↔ 1).
- Complement each literal in the result.
Example: F = A'B'C + AB + AC'
Dual of F: (A' + B' + C)(A + B)(A + C')
Complement every literal:
F' = (A + B + C')(A' + B')(A' + C)
Same answer as Method 1 ✓.
14.3 Method 3: Use the canonical forms
- If
F = Σm(list), thenF' = Σm(the remaining rows). - If
F = ΠM(list), thenF' = ΠM(the remaining rows). - You can also switch type: the complement of Σm(list) is ΠM(list) using the same numbers.
Using the function from section 13: F = Σm(1, 4, 6, 7) = ΠM(0, 2, 3, 5).
F' = Σm(0, 2, 3, 5)
= A'B'C' + A'BC' + A'BC + AB'C
F' = ΠM(1, 4, 6, 7)
= (A + B + C')(A' + B + C)(A' + B' + C)(A' + B' + C')
Why it works: Σm(list) ORs minterms. Complementing it with De Morgan gives the AND of each (mᵢ)', and (mᵢ)' = Mᵢ. So [Σm(1,4,6,7)]' = M₁ · M₄ · M₆ · M₇ = ΠM(1,4,6,7).
14.4 Verifying with the truth table
For the function in section 13, F' = 1 exactly in rows 0, 2, 3, 5 (where F was 0), which matches Σm(0, 2, 3, 5).
14.5 Complementing a simple example step by step
F = AB' + C
F' = (AB' + C)'
= (AB')' · C' (Theorem 2)
= (A' + B) · C' (Theorem 1 and involution)
= A'C' + BC' (distributive law, giving SOP)
14.6 Common mistakes when complementing
- Writing
(A + B)' = A' + B'. Wrong! It must beA'B'. - Forgetting to complement the literals, not just swapping AND/OR (this gives the dual, not the complement).
- Dropping parentheses when a bar covers a group, so the operator precedence changes.
Quick Revision Cheat Sheet
All the laws in one place
| Name | AND form | OR form |
|---|---|---|
| Identity | A·1 = A | A+0 = A |
| Null | A·0 = 0 | A+1 = 1 |
| Idempotent | A·A = A | A+A = A |
| Complement | A·A' = 0 | A+A' = 1 |
| Involution | (A')' = A | |
| Commutative | AB = BA | A+B = B+A |
| Associative | (AB)C = A(BC) | (A+B)+C = A+(B+C) |
| Distributive | A(B+C) = AB+AC | A+BC = (A+B)(A+C) |
| Absorption | A(A+B) = A | A+AB = A |
| Useful extra | A(A'+B) = AB | A+A'B = A+B |
| De Morgan | (AB)' = A'+B' | (A+B)' = A'B' |
Forms at a glance
| Form | Structure | Built from | Notation |
|---|---|---|---|
| SOP | OR of ANDs | rows with F = 1 | Σm(...) |
| POS | AND of ORs | rows with F = 0 | ΠM(...) |
Minterm mᵢ | AND of all variables | is 1 only on row i | 1 → plain, 0 → complemented |
Maxterm Mᵢ | OR of all variables | is 0 only on row i | 1 → complemented, 0 → plain |
Key relationships
Mᵢ = (mᵢ)' mᵢ = (Mᵢ)'
F = Σm(ones) = ΠM(zeros)
F' = Σm(zeros) = ΠM(ones)
Dual: swap AND/OR and 0/1 (keep variables)
Complement: dual, then complement every literal
Common mistakes to avoid
- Reading
+as arithmetic addition (1 + 1 = 1, not 2). - Mixing up dual and complement.
- Applying De Morgan as
(A+B)' = A'+B'(the correct result isA'B'). - Using the wrong rule for maxterms (they are complemented where the bit is 1, the opposite of minterms).
- Forgetting to remove duplicate terms after expanding to canonical form.
- Not listing the canonical terms for all missing variables when expanding.
One-line summary of each topic
| Topic | In one line |
|---|---|
| Variables, operators, expressions | 0/1 values combined with NOT, AND and OR |
| Identity, null, idempotent, complement | How constants and repeated or opposite variables behave |
| Commutative, associative, distributive | Reordering, regrouping and expanding or factoring |
| Absorption and involution | A big term swallowed by a small one; double NOT cancels |
| De Morgan's theorems | Complementing a product gives a sum of complements, and vice versa |
| Duality | Swap AND/OR and 0/1 and the law still holds |
| Simplification | Apply the laws to reach a smaller equivalent expression |
| SOP / POS | OR of ANDs / AND of ORs |
| Minterms / maxterms | Full-variable AND terms (true on one row) / OR terms (false on one row) |
| Canonical SOP / POS | Σm over the 1-rows / ΠM over the 0-rows |
| Truth table → expression | Write a term for each 1-row (SOP) or 0-row (POS) |
| Complementation | De Morgan, dual-then-complement, or swap the row lists |
##Logic Minimization Techniques#
What this note is about: A Boolean function can be written in many equivalent ways, but some ways need far fewer gates than others. Logic minimization is the art (and science) of finding the cheapest correct expression. These notes walk through every major technique, from plain algebra to the Quine–McCluskey table method, and end with the catch: minimization can introduce hazards.
Table of Contents
- Why Minimize at All?
- Algebraic Simplification
- Karnaugh Maps (K-maps): The Big Idea
- Two-Variable and Three-Variable K-maps
- Four-Variable K-maps
- Five- and Six-Variable Minimization Concepts
- Grouping Adjacent Cells (The Rules)
- Prime Implicants and Essential Prime Implicants
- Don't-Care Conditions
- SOP and POS Minimization
- Quine–McCluskey Tabulation Method
- Hazards Introduced by Logic Minimization
- Quick Revision Cheat Sheet
1. Why Minimize at All?
Every gate costs area, power, delay and money. A smaller expression usually means:
- fewer gates and fewer gate inputs,
- fewer interconnections,
- often a faster circuit (fewer levels of logic),
- easier testing and debugging.
What does "minimal" mean? For two-level (AND-OR or OR-AND) circuits, the usual goal is:
- Fewest product terms (for SOP) or sum terms (for POS), then
- Fewest literals (a literal is a variable or its complement, like
AorA').
A function can have more than one minimal form. "Minimal" does not always mean "unique".
Terms you will see everywhere
| Term | Meaning | Example |
|---|---|---|
| Literal | A variable or its complement | A, B' |
| Minterm | Product term containing every variable once; equals 1 for exactly one input row | A'BC = m3 (for 3 variables) |
| Maxterm | Sum term containing every variable once; equals 0 for exactly one input row | A+B'+C = M2 |
| SOP | Sum of Products (OR of ANDs) | AB + A'C |
| POS | Product of Sums (AND of ORs) | (A+B)(A'+C) |
| Implicant | Any product term that implies the function (covers only 1s) | AB |
2. Algebraic Simplification
This is minimization using Boolean algebra laws directly, with no maps and no tables. It is flexible and works for any number of variables, but it relies on your ability to spot the right move.
2.1 The toolbox
| Law | SOP form | Dual (POS) form |
|---|---|---|
| Identity | A + 0 = A | A · 1 = A |
| Null / Domination | A + 1 = 1 | A · 0 = 0 |
| Idempotent | A + A = A | A · A = A |
| Complement | A + A' = 1 | A · A' = 0 |
| Commutative | A + B = B + A | AB = BA |
| Associative | (A+B)+C = A+(B+C) | (AB)C = A(BC) |
| Distributive | A(B+C) = AB + AC | A + BC = (A+B)(A+C) |
| Absorption | A + AB = A | A(A+B) = A |
| Simplification (a.k.a. redundancy) | A + A'B = A + B | A(A'+B) = AB |
| Adjacency / Combining | AB + AB' = A | (A+B)(A+B') = A |
| De Morgan | (A+B)' = A'B' | (AB)' = A'+B' |
| Consensus | AB + A'C + BC = AB + A'C | (A+B)(A'+C)(B+C) = (A+B)(A'+C) |
2.2 Worked examples
Example 1: Combining + absorption
F = A'B'C + A'BC + AB'C + ABC
= A'C(B' + B) + AC(B' + B) (factor)
= A'C + AC (B + B' = 1)
= C(A' + A)
= C
Example 2: The "A + A'B = A + B" trick
F = A + A'B + A'B'C
= A + B + A'B'C (A + A'B = A + B)
= A + B + B'C (A'B'C, but A already absorbs A', so A + A'X = A + X)
= A + B + C (B + B'C = B + C)
Example 3: Consensus theorem (removing a redundant term)
F = AB + A'C + BC
BC is the consensus of AB and A'C (the variable A appears in both forms, and what remains is B and C). The consensus term is redundant:
F = AB + A'C
2.3 Strengths and weaknesses
| Pros | Cons |
|---|---|
| Works for any number of variables | No guarantee you reached the minimum |
| No tables or maps needed | Depends on spotting the right law at the right time |
| Great for quick, small simplifications | Hard to apply systematically (and hard to automate) |
Why this matters: These limitations are exactly why K-maps and Quine–McCluskey were invented. They make the process systematic.
3. Karnaugh Maps (K-maps): The Big Idea
A K-map is a graphical way to lay out a truth table so that cells that differ by exactly one variable sit next to each other.
3.1 Why does adjacency matter?
Because of the combining law XY + XY' = X. Two minterms that differ in exactly one variable can be merged, and that variable disappears. A K-map just puts such pairs side by side so your eyes can spot them.
3.2 The Gray code secret
Rows and columns of a K-map are labelled in Gray code (00, 01, 11, 10) and not in binary order (00, 01, 10, 11). Gray code changes only one bit between neighbours, which guarantees the adjacency property.
Binary order: 00 → 01 → 10 → 11 (01 → 10 changes TWO bits ✗)
Gray order: 00 → 01 → 11 → 10 (each step changes ONE bit ✓)
3.3 Key properties
- A map for n variables has 2ⁿ cells, one per minterm.
- The map is wrap-around: the left edge touches the right edge, and the top edge touches the bottom edge (think of it as drawn on a doughnut/torus). The four corners are all mutually adjacent in a 4-variable map.
- A group of 2ᵏ adjacent cells eliminates k variables.
| Group size | Variables eliminated (n-var map) | Literals left in the term |
|---|---|---|
| 1 cell | 0 | n |
| 2 cells | 1 | n − 1 |
| 4 cells | 2 | n − 2 |
| 8 cells | 3 | n − 3 |
| 16 cells | 4 | n − 4 |
3.4 General K-map workflow
- Draw the map and label the axes in Gray code.
- Fill in 1s (for minterms), 0s (for maxterms), and X (for don't-cares).
- Make the largest possible groups of 1s (sizes 1, 2, 4, 8, ...).
- Cover every 1 with as few groups as possible.
- Write a product term per group: keep variables that stay constant across the group, drop those that change.
- OR all product terms together.
4. Two-Variable and Three-Variable K-maps
4.1 Two-variable K-map (4 cells)
B=0 B=1
A=0 | m0 | m1 |
A=1 | m2 | m3 |
Example: F(A,B) = Σm(1,2,3)
B=0 B=1
A=0 | 0 | 1 |
A=1 | 1 | 1 |
- Group
m1, m3(B = 1 in both) →B - Group
m2, m3(A = 1 in both) →A
Result: F = A + B
Two-variable maps are so small they are mostly for learning. Algebra is just as fast here.
4.2 Three-variable K-map (8 cells)
Rows: A. Columns: BC in Gray order.
BC=00 BC=01 BC=11 BC=10
A=0 | m0 | m1 | m3 | m2 |
A=1 | m4 | m5 | m7 | m6 |
Remember: column 00 and column 10 are neighbours (wrap-around), so m0 is adjacent to m2, and m4 is adjacent to m6.
Example A: simple grouping
F(A,B,C) = Σm(1,3,5,7)
BC=00 BC=01 BC=11 BC=10
A=0 | 0 | 1 | 1 | 0 |
A=1 | 0 | 1 | 1 | 0 |
One group of 4 (the two middle columns). C = 1 throughout, while A and B both vary.
Result: F = C
Example B: wrap-around
F(A,B,C) = Σm(0,2,4,6)
BC=00 BC=01 BC=11 BC=10
A=0 | 1 | 0 | 0 | 1 |
A=1 | 1 | 0 | 0 | 1 |
The outer columns wrap around to form one group of 4. C = 0 throughout.
Result: F = C'
Example C: a map with no essential prime implicants (cyclic)
F(A,B,C) = Σm(0,1,2,5,6,7)
BC=00 BC=01 BC=11 BC=10
A=0 | 1 | 1 | 0 | 1 |
A=1 | 0 | 1 | 1 | 1 |
Every 1 sits in two possible pairs, so nothing is forced. There are two equally good answers:
F = A'B' + BC' + AC
F = A'C' + B'C + AB
Both need 3 terms and 6 literals. This is the classic "pick any consistent cover" situation (more in Section 8).
5. Four-Variable K-maps
This is the workhorse of manual minimization. 16 cells; rows AB, columns CD, both in Gray order.
CD=00 CD=01 CD=11 CD=10
AB=00 | m0 | m1 | m3 | m2 |
AB=01 | m4 | m5 | m7 | m6 |
AB=11 | m12 | m13 | m15 | m14 |
AB=10 | m8 | m9 | m11 | m10 |
5.1 Legal group shapes
| Size | Possible shapes |
|---|---|
| 1 | single cell |
| 2 | horizontal pair, vertical pair (including wrap-around pairs) |
| 4 | a row, a column, a 2×2 square, 2×2 wrap-around blocks, the four corners |
| 8 | two adjacent rows, two adjacent columns (including the wrapped outer pair) |
| 16 | the whole map (F = 1) |
5.2 Worked example
F(A,B,C,D) = Σm(0,1,2,5,8,9,10)
CD=00 CD=01 CD=11 CD=10
AB=00 | 1 | 1 | 0 | 1 |
AB=01 | 0 | 1 | 0 | 0 |
AB=11 | 0 | 0 | 0 | 0 |
AB=10 | 1 | 1 | 0 | 1 |
Groups:
| Group | Cells | What stays constant | Term |
|---|---|---|---|
| Four corners | m0, m2, m8, m10 | B = 0, D = 0 | B'D' |
| Left-two-columns of top/bottom rows | m0, m1, m8, m9 | B = 0, C = 0 | B'C' |
| Vertical pair | m1, m5 | A = 0, C = 0, D = 1 | A'C'D |
Result:
F = B'D' + B'C' + A'C'D
Why that third group is a pair and not bigger: m5's only neighbouring 1 is m1 (m4, m7 and m13 are 0). Always try to enlarge, but only as far as the map allows.
5.3 Reading a term off a group: a mini recipe
For each variable ask: "Does this variable have the same value in every cell of the group?"
- Yes, and it is
1→ write the variable (A). - Yes, and it is
0→ write the complement (A'). - No (it changes) → leave it out.
6. Five- and Six-Variable Minimization Concepts
You cannot draw a flat 2D grid where every neighbour differs by only one bit beyond four variables, so we use stacked layers.
6.1 Five-variable maps
Draw two 4-variable maps side by side (or stacked), one for E = 0 and one for E = 1 (taking A as the extra variable works equally well, as long as you are consistent).
Layer E=0 Layer E=1
CD: 00 01 11 10 CD: 00 01 11 10
AB=00 | m0 m1 m3 m2 | AB=00 | m16 m17 m19 m18 |
AB=01 | m4 m5 m7 m6 | AB=01 | m20 m21 m23 m22 |
AB=11 | m12 m13 m15 m14| AB=11 | m28 m29 m31 m30 |
AB=10 | m8 m9 m11 m10| AB=10 | m24 m25 m27 m26 |
Adjacency rules:
- Within a layer: same as an ordinary 4-variable map (including wrap-around).
- Between layers: a cell is adjacent to the cell in the same position in the other layer (think of the layers as transparent sheets laid on top of each other, or as one layer being the mirror image of the other).
- Groups can be built across both layers, and the variable
Eis simply dropped from that term.
Example idea: m5 (E=0) and m21 (E=1) sit in the same position → they combine to eliminate E.
6.2 Six-variable maps
Use four 4-variable layers, labelled by the two extra variables (say E and F) in Gray order: EF = 00, 01, 11, 10.
Layer order (Gray): 00 → 01 → 11 → 10 → (wraps back to 00)
Adjacency rules:
- Within a layer: as usual.
- Between layers: the same position in two layers that are neighbours in the Gray sequence are adjacent. That means
00↔01,01↔11,11↔10, and the wrap10↔00. Layers00and11are not adjacent (they differ in two bits). - A group may span 1, 2 or 4 layers, so group sizes can reach 32 or 64.
6.3 Why people stop using K-maps here
| Issue | Detail |
|---|---|
| Visualization | Tracking adjacency across layers by eye becomes error-prone |
| Cell count | 32 cells (5-var) and 64 cells (6-var) are a lot to scan |
| Beyond 6 variables | Impractical; the map no longer helps |
Takeaway: K-maps are the tool for up to 4 variables comfortably, 5-6 with care. For more variables, use the systematic tabular method (Section 11), which is easy to turn into a computer program.
7. Grouping Adjacent Cells (The Rules)
Getting the grouping right is 90% of K-map skill. Learn these rules and the rest follows.
7.1 The rules
- Group only 1s (when minimizing for SOP). Never include a 0. (An X may be included, see Section 9.)
- Group sizes must be powers of 2: 1, 2, 4, 8, 16, ...
- Groups must be rectangular (squares included) and made of adjacent cells. Diagonal groups are illegal.
- Make groups as large as possible. Bigger group = fewer literals.
- Use as few groups as possible to cover all the 1s.
- Groups may overlap. Reusing a 1 in more than one group is fine, and often necessary.
- Every 1 must be covered by at least one group.
- Wrap-around counts: edges and corners are neighbours.
7.2 Good vs. bad grouping
CD=00 CD=01 CD=11 CD=10
AB=00 | 1 | 1 | 0 | 0 |
AB=01 | 1 | 1 | 0 | 0 |
AB=11 | 0 | 0 | 0 | 0 |
AB=10 | 0 | 0 | 0 | 0 |
| Grouping | Result | Verdict |
|---|---|---|
Two vertical pairs: {m0,m4} and {m1,m5} | A'C'D' + A'C'D | ✗ Not maximal |
One 2×2 square {m0,m1,m4,m5} | A'C' | ✓ Minimal |
7.3 Common mistakes
| Mistake | Why it is wrong |
|---|---|
| Groups of 3, 5, 6 | Sizes must be powers of 2 |
| Diagonal groups | Diagonal cells differ in two variables |
| Forgetting wrap-around | You miss larger groups (e.g., the four corners) |
| Stopping at a small group when a larger one exists | Leaves unnecessary literals |
| Using redundant groups | A group whose cells are all already covered by other chosen groups adds cost for nothing |
| Binary-ordering the axes | Breaks the adjacency property |
8. Prime Implicants and Essential Prime Implicants
These two ideas turn "make good groups" into a precise, checkable procedure. They are also the foundation for Quine–McCluskey.
8.1 Definitions
| Term | Definition | On the K-map |
|---|---|---|
| Implicant | A product term whose 1s all belong to the function | Any legal group of 1s (any size) |
| Prime Implicant (PI) | An implicant that cannot be enlarged (no variable can be removed without covering a 0) | A group that is not contained inside any larger legal group |
| Essential Prime Implicant (EPI) | A PI that is the only PI covering at least one particular minterm | A PI that covers some 1 no other PI covers |
| Non-essential (selective) PI | A PI that is not essential | Optional; chosen only if needed to finish the cover |
8.2 Step-by-step procedure
- Find all prime implicants (every maximal group).
- Identify essential prime implicants: for each 1, check whether only one PI covers it. If so, that PI is essential and must be in the answer.
- Include all EPIs and mark every 1 they cover.
- Cover the remaining 1s (if any) with the fewest, cheapest non-essential PIs.
- Write the final SOP: EPIs + chosen extras.
8.3 Example (all PIs essential)
Using the function from Section 5.2, F = Σm(0,1,2,5,8,9,10):
| Minterm | PIs covering it |
|---|---|
| m0 | B'D', B'C' |
| m1 | B'C', A'C'D |
| m2 | B'D' ← only one |
| m5 | A'C'D ← only one |
| m8 | B'D', B'C' |
| m9 | B'C' ← only one |
| m10 | B'D' ← only one |
Because m2, m5, m9 are each covered by a single PI, all three PIs are essential, so F = B'D' + B'C' + A'C'D is the one and only minimal SOP.
8.4 Example (no essential PIs: cyclic)
In Section 4.2 (Example C) every minterm was covered by two PIs, so no PI is essential. You then have to choose. There may be several equally minimal answers. This is called a cyclic (or "cyclic prime implicant table") situation.
8.5 Quick intuition
PI = "a group I cannot grow any bigger." EPI = "a group I cannot live without."
9. Don't-Care Conditions
9.1 What are they?
Sometimes certain input combinations:
- never occur (e.g., BCD uses only 0-9, so inputs 10-15 never appear), or
- occur but we do not care what the output is.
For these inputs, the output can be freely chosen as 0 or 1. We mark them X (or d) in the truth table and K-map.
9.2 How to use them
- Treat each
Xas a joker: include it in a group if it helps make that group larger, and ignore it otherwise. - You do not need to cover X cells. Only the real 1s must be covered.
- An X that ends up inside a group is effectively assigned the value 1; an X left outside is effectively 0.
- Never form a group made only of X cells (it would add a term for no reason).
9.3 Worked example
F(A,B,C,D) = Σm(1,3,7,11,15) + d(0,2,5)
CD=00 CD=01 CD=11 CD=10
AB=00 | X | 1 | 1 | X |
AB=01 | 0 | X | 1 | 0 |
AB=11 | 0 | 0 | 1 | 0 |
AB=10 | 0 | 0 | 1 | 0 |
- Group
{m0, m1, m3, m2}(using X at m0, m2) →A'B' - Group
{m3, m7, m11, m15}(the wholeCD=11column) →CD
Result:
F = A'B' + CD
Without don't-cares, you would need smaller groups and more literals. Don't-cares simplify the circuit.
9.4 Things to remember
| Point | Detail |
|---|---|
| Designer's freedom | Don't-cares are a gift: use them to enlarge groups |
| Not always used | If an X doesn't help, treat it as 0 |
| Works for POS too | In POS minimization, X cells can join groups of 0s |
| Caution | Actual hardware will output something for a don't-care input; that behaviour is simply unspecified/unimportant |
10. SOP and POS Minimization
The same function can be expressed two ways. Which one do you minimize?
10.1 Minimal SOP (Sum of Products)
- Group the 1s on the K-map.
- Each group → a product term (variable = 1 →
A, variable = 0 →A'). - OR the terms together.
- Circuit: AND gates feeding an OR gate.
10.2 Minimal POS (Product of Sums)
- Group the 0s on the K-map.
- Each group → a sum term, and here the polarity is flipped: variable = 0 →
A, variable = 1 →A'. - AND the sum terms together.
- Circuit: OR gates feeding an AND gate.
Why the flip? Grouping 0s first gives F' as a minimal SOP. Applying De Morgan's law to F' converts it into POS for F.
10.3 Worked example (same function, both forms)
F = Σm(0,1,2,5,8,9,10), so the 0s are at m3, m4, m6, m7, m11, m12, m13, m14, m15.
CD=00 CD=01 CD=11 CD=10
AB=00 | 1 | 1 | 0 | 1 |
AB=01 | 0 | 1 | 0 | 0 |
AB=11 | 0 | 0 | 0 | 0 |
AB=10 | 1 | 1 | 0 | 1 |
Group the 0s:
| Group (0s) | Cells | Product term for F' |
|---|---|---|
CD=11 column | m3, m7, m11, m15 | CD |
Right/left wrap, rows 01 & 11 | m4, m6, m12, m14 | BD' |
AB=11 row | m12, m13, m14, m15 | AB |
So:
F' = CD + BD' + AB
Apply De Morgan:
F = (CD + BD' + AB)'
= (C' + D')(B' + D)(A' + B')
Compare the two minimal forms:
| Form | Expression | Terms | Literals |
|---|---|---|---|
| SOP | B'D' + B'C' + A'C'D | 3 | 7 |
| POS | (C'+D')(B'+D)(A'+B') | 3 | 6 |
Here POS is slightly cheaper in literals. In other functions SOP will win. Neither is always better.
10.4 Which should I pick?
| Situation | Better choice |
|---|---|
| Fewer 1s than 0s | SOP (fewer groups to draw) |
| Fewer 0s than 1s | POS |
| Implementation uses NAND-NAND logic | SOP |
| Implementation uses NOR-NOR logic | POS |
| Not sure | Do both and compare cost |
10.5 Cheat sheet: reading polarity
| SOP (group 1s) | POS (group 0s) | |
|---|---|---|
| Variable constant at 1 | A | A' |
| Variable constant at 0 | A' | A |
| Within one group | variables ANDed | variables ORed |
| Across groups | OR | AND |
11. Quine–McCluskey Tabulation Method
Also called the tabular method. It does the same job as a K-map (find all prime implicants, then pick a minimal cover), but follows a fixed algorithm, so it works for any number of variables and is easy to program.
11.1 Big picture
Step 1: List minterms (and don't-cares) in binary
Step 2: Group them by number of 1s
Step 3: Repeatedly combine pairs that differ in exactly ONE bit → replace that bit with "-"
Step 4: Terms that can no longer be combined are PRIME IMPLICANTS
Step 5: Build a prime implicant chart; pick essential PIs
Step 6: Cover any leftover minterms with the fewest extra PIs
11.2 Worked example
F(A,B,C,D) = Σm(0,1,2,5,8,9,10) (same function as before, so you can compare with the K-map answer).
Step 1 and 2: Group by number of 1s
| Group | Minterm | Binary (ABCD) |
|---|---|---|
| 0 ones | 0 | 0000 |
| 1 one | 1 | 0001 |
| 2 | 0010 | |
| 8 | 1000 | |
| 2 ones | 5 | 0101 |
| 9 | 1001 | |
| 10 | 1010 |
Step 3a: First combining pass (compare adjacent groups only; combine if they differ in exactly one bit)
| Pair | Result | Mark ✓ |
|---|---|---|
| 0, 1 | 000- | 0 ✓, 1 ✓ |
| 0, 2 | 00-0 | 2 ✓ |
| 0, 8 | -000 | 8 ✓ |
| 1, 5 | 0-01 | 5 ✓ |
| 1, 9 | -001 | 9 ✓ |
| 2, 10 | -010 | 10 ✓ |
| 8, 9 | 100- | |
| 8, 10 | 10-0 |
Step 3b: Second combining pass. Only terms with the dash in the same position can combine.
| Pair | Result |
|---|---|
000- (0,1) + 100- (8,9) | -00- → (0,1,8,9) |
00-0 (0,2) + 10-0 (8,10) | -0-0 → (0,2,8,10) |
-000 (0,8) + -001/-010 | dash positions match but can't produce anything new (duplicates of the above) |
Term 0-01 (1,5) has no partner → it stays.
Step 4: Prime implicants
| PI | Minterms | Product term |
|---|---|---|
-00- | 0, 1, 8, 9 | B'C' |
-0-0 | 0, 2, 8, 10 | B'D' |
0-01 | 1, 5 | A'C'D |
Step 5: Prime implicant chart (× = PI covers that minterm)
| PI | m0 | m1 | m2 | m5 | m8 | m9 | m10 |
|---|---|---|---|---|---|---|---|
B'C' | × | × | × | × | |||
B'D' | × | × | × | × | |||
A'C'D | × | × |
Columns with a single × identify essential PIs:
m2→ onlyB'D'✓ essentialm5→ onlyA'C'D✓ essentialm9→ onlyB'C'✓ essential
All minterms are now covered.
Final answer:
F = B'C' + B'D' + A'C'D
It matches the K-map result.
11.3 Handling don't-cares in Q-M
- Include don't-care minterms in Steps 1-4, so they help form bigger implicants.
- Exclude them from the columns of the PI chart in Step 5, because they do not need to be covered.
11.4 Resolving a cyclic chart
If no essential PIs exist, or some minterms remain after picking essentials:
- Row dominance: if row X covers everything row Y covers (and costs no more), drop row Y.
- Column dominance: if column p has all the ×s that column q has, drop the column that is covered by the other's rows (the column with more ×s is the easier one and can be removed).
- If still stuck, try a PI (branching) and see which choice gives the lowest total cost (Petrick's method is the formal version of this idea).
11.5 K-map vs. Quine–McCluskey
| Aspect | K-map | Quine–McCluskey |
|---|---|---|
| Style | Visual, intuitive | Tabular, algorithmic |
| Practical variable limit | About 4-6 | Large (limited by computation, not by eyesight) |
| Human error | Easy to miss a group | Systematic, less guesswork |
| Computer-friendly | No | Yes |
| Speed for small problems | Faster | Slower, lots of bookkeeping |
| Finds all PIs guaranteed? | Only if you look carefully | Yes, by construction |
Limitation to remember: the number of prime implicants can grow very quickly with the number of variables, so even Q-M becomes heavy for large functions.
12. Hazards Introduced by Logic Minimization
Minimization removes "redundant" terms. Great for cost, but those redundant terms sometimes exist to keep the output steady. Removing them can create hazards.
12.1 What is a hazard?
A hazard is the possibility of a momentary, unwanted glitch (spike) at the output when inputs change, caused by unequal gate delays along different signal paths. The final settled value is correct. It is only the transition that misbehaves.
Hazard = potential for a glitch. Glitch = the actual spike that appears.
12.2 Types
| Type | Output should stay | But glitches to | Typical cause |
|---|---|---|---|
| Static-1 hazard | 1 | 0 briefly (1 → 0 → 1) | Two adjacent 1s in different product terms with no common covering term |
| Static-0 hazard | 0 | 1 briefly (0 → 1 → 0) | Two adjacent 0s in different sum terms with no common covering term |
| Dynamic hazard | Should change once (0→1 or 1→0) | Changes 3 or more times (e.g., 0 → 1 → 0 → 1) | Multiple paths in multi-level logic |
12.3 Static-1 hazard: the classic example
F = AB + A'C
Set B = 1, C = 1. Then F = A + A' = 1 regardless of A. Now flip A from 1 to 0.
┌──────────────┐
A ──►│ AND (AB) ├──┐
B ──►│ │ │ ┌────┐
└──────────────┘ ├────►│ OR ├──► F
A ─►NOT─►┌───────────┐ │ └────┘
C ──────►│ AND (A'C) ├──┘
└───────────┘
ABdrops from 1 to 0 asAfalls.A'Crises from 0 to 1 but only after the NOT gate's delay.- For a brief moment, both AND outputs are 0 →
Fglitches to 0.
On the K-map:
BC=00 BC=01 BC=11 BC=10
A=0 | 0 | 1 | 1 | 0 | ← m1, m3 grouped as A'C
A=1 | 0 | 0 | 1 | 1 | ← m6, m7 grouped as AB
m3 (A=0, B=1, C=1) and m7 (A=1, B=1, C=1) are adjacent 1s but sit in two different groups. The glitch happens exactly when the input moves across the boundary between the two groups.
12.4 The fix: add the consensus term
Add a group that bridges the two:
F = AB + A'C + BC
The extra BC term stays at 1 throughout the change, holding the output steady.
Notice the irony: this is the redundant term the consensus theorem told us to throw away in Section 2.2 (Example 3). Minimal ≠ hazard-free.
12.5 Static-0 hazards (POS circuits)
By duality, a POS circuit such as F = (A + B)(A' + C) can glitch when B = C = 0 and A changes (output should stay 0). Fix by adding the redundant sum term (B + C):
F = (A + B)(A' + C)(B + C)
12.6 Rules of thumb
| Rule | Detail |
|---|---|
| Condition for hazard-free two-level SOP (single-input change) | Every pair of adjacent 1s must be covered by at least one common product term |
| Hazard-free two-level POS | Every pair of adjacent 0s must share a common sum term |
| Two-level AND-OR circuits | Can have static-1 hazards, but no static-0 or dynamic hazards (for a single input change) |
| Two-level OR-AND circuits | Can have static-0 hazards, but no static-1 or dynamic hazards |
| Multi-level circuits | May show all three kinds |
| Scope | The standard analysis is for one input changing at a time |
12.7 How to find hazards on a K-map
- Draw the minimal SOP groups.
- Look for adjacent 1s that are in different groups with no group containing both.
- Each such pair is a static-1 hazard.
- Add a redundant (bridging) group covering both cells to remove it.
12.8 Does it always matter?
- In purely synchronous designs, glitches usually settle before the next clock edge, so they are harmless unless the glitching signal drives something sensitive.
- They matter a lot when the signal feeds asynchronous inputs: clock lines, set/reset lines, latch enables, or asynchronous sequential circuits, where a glitch can cause false triggering.
12.9 The trade-off
Fewer gates, fewer literals ◄───────────► Glitch-free behaviour
(minimal) (extra redundant terms)
Designers consciously give up minimality in the places where a glitch would cause real damage.
13. Quick Revision Cheat Sheet
Methods at a glance
| Method | Best for | Strength | Weakness |
|---|---|---|---|
| Algebraic simplification | Small expressions, any variable count | Flexible, no tools | Not systematic; minimality not guaranteed |
| K-map | 2-4 variables (5-6 with care) | Visual, fast | Doesn't scale |
| Quine–McCluskey | Many variables, computer implementation | Systematic, guaranteed all PIs | Tedious by hand; PI count can explode |
K-map must-remember list
- Axes in Gray code (
00, 01, 11, 10). - Groups: rectangles of size 2ᵏ, as large as possible, as few as possible.
- Group of 2ᵏ cells eliminates k variables.
- Edges and corners wrap around.
- Overlap is allowed; diagonals are not.
- 5-var: 2 layers (same-position cells are adjacent). 6-var: 4 layers (Gray-adjacent layers only).
Prime implicant vocabulary
- PI: cannot be enlarged.
- EPI: the only PI covering some minterm, so it is mandatory.
- Cyclic table: no EPIs, so you must choose.
Don't-cares
X= free choice. Use it only to enlarge groups. It never needs covering.
SOP vs. POS
| SOP | POS | |
|---|---|---|
| Group | 1s | 0s |
| Term polarity | 1 → A, 0 → A' | 0 → A, 1 → A' |
| Gates | AND-OR | OR-AND |
Hazards
- Static-1: adjacent 1s, different groups, glitch 1→0→1. Fix: add the bridging (consensus) term.
- Static-0: adjacent 0s, glitch 0→1→0. Fix: add the bridging sum term.
- Minimization can create hazards; hazard-free design may need redundant terms.
#Combinational Logic Circuits#
#Sequential Logic Circuits#
##Sequential Circuit Fundamentals#
Study notes that take you from "what even makes a circuit sequential?" all the way to metastability and synchronizers. Read top to bottom the first time; use the cheat sheet at the end for revision.
Table of Contents
- Combinational vs Sequential Circuits
- State, Memory and Feedback
- Clock Signals and Clock Edges
- Synchronous vs Asynchronous Circuits
- Timing Diagrams
- State Tables and State Diagrams
- Latches vs Flip-Flops
- Setup Time, Hold Time and Propagation Delay
- Clock Skew and Clock Jitter
- Metastability and Synchronizers
- Quick Revision Cheat Sheet
1. Combinational vs Sequential Circuits
The one-line difference
- Combinational circuit: output depends only on the current inputs.
- Sequential circuit: output depends on the current inputs and the past history of inputs (what the circuit "remembers").
An everyday analogy
- A calculator's adder is combinational: type 2 + 3 and you get 5, always, no matter what you did before.
- A door lock with a keypad code is sequential: pressing "7" means different things depending on whether you already pressed "3-1" before it.
Side-by-side comparison
| Feature | Combinational | Sequential |
|---|---|---|
| Output depends on | Present inputs only | Present inputs + stored state |
| Memory elements | None | Latches / flip-flops |
| Feedback path | No | Yes (state fed back) |
| Clock needed? | No | Usually yes (synchronous) |
| Speed | Generally faster (no storage overhead) | Slightly slower (clock + storage delays) |
| Design tools | Truth table, Boolean algebra, K-map | State table, state diagram, timing diagram |
| Examples | Adder, multiplexer, decoder, encoder, comparator | Counter, register, shift register, FSM, memory |
Block diagrams
COMBINATIONAL
Inputs ───► [ Combinational Logic ] ───► Outputs
SEQUENTIAL
┌────────────────────────────────┐
│ Next State │
Inputs ───► │ (Combinational Logic) │ ───► Outputs
│ │
└───────▲────────────┬───────────┘
│ │ next state
present │ ▼
state │ [ Memory (flip-flops) ] ◄── Clock
└────────────┘
Key idea: a sequential circuit = combinational logic + memory + feedback loop.
2. State, Memory and Feedback
2.1 What is "state"?
State is a snapshot of everything the circuit needs to remember in order to predict its future behaviour, given future inputs.
- A 2-bit counter has 4 possible states:
00, 01, 10, 11. - A circuit with n flip-flops can have up to 2ⁿ states.
2.2 What is "memory"?
Memory elements hold a bit (0 or 1) even after the input that set it has gone away. In sequential circuits, the basic memory elements are:
- Latches (level-sensitive)
- Flip-flops (edge-triggered)
Each one stores 1 bit. Group them together and you get registers.
2.3 What is "feedback"?
Feedback means an output (or the stored state) is routed back as an input. This is what lets a circuit "hold on" to a value.
The simplest memory cell is two cross-coupled NOR (or NAND) gates:
┌──────────────┐
S ────►│ NOR ├──── Q
│ │ ▲
└──────▲───────┘ │
│ │ (cross-coupled feedback)
┌──────┴───────┐ │
R ────►│ NOR ├─┘──── Q'
└──────────────┘
Each gate's output feeds the other gate's input. This loop has two stable configurations (Q=0 or Q=1), so it can remember one bit. This is called a bistable element.
2.4 Present state vs Next state
| Term | Meaning |
|---|---|
| Present state (Q) | What the memory currently holds |
| Next state (Q⁺ or Q(t+1)) | What the memory will hold after the next clock event |
| Excitation / next-state logic | Combinational logic that computes the next state from inputs + present state |
| Output logic | Combinational logic that computes the outputs |
2.5 Why feedback is double-edged
- Good: it creates memory.
- Risky: uncontrolled feedback can cause oscillation or unpredictable behaviour. That is why we use disciplined elements (flip-flops) and a clock to control when feedback is allowed to change state.
3. Clock Signals and Clock Edges
3.1 What is a clock?
A clock is a periodic square-wave signal that acts like a metronome for the circuit. It tells every flip-flop when it is allowed to update.
┌───┐ ┌───┐ ┌───┐ ┌───┐
CLK ───┘ └───┘ └───┘ └───┘ └───
◄── T ──►
3.2 Clock parameters
| Term | Meaning |
|---|---|
| Period (T) | Time for one full cycle |
| Frequency (f) | f = 1 / T (in Hz) |
| Duty cycle | (High time / T) × 100%. A 50% duty cycle means equal high and low time |
| Clock cycle | One complete period of the clock |
Example: f = 100 MHz → T = 1 / 100×10⁶ = 10 ns.
3.3 Clock edges and levels
┌─────────┐
│ │
─────────┘ └─────────
▲ ▲
rising edge falling edge
(positive) (negative)
◄─ HIGH level ─► ◄─ LOW level ─►
- Rising / positive edge: transition
0 → 1 - Falling / negative edge: transition
1 → 0 - Level: the steady HIGH (1) or LOW (0) portion between edges
3.4 Triggering styles
| Type | When the memory element reacts |
|---|---|
| Level-triggered | The whole time the clock is at a certain level (HIGH or LOW). Used by latches |
| Positive-edge-triggered | Only at the instant of the rising edge. Used by flip-flops |
| Negative-edge-triggered | Only at the instant of the falling edge. Used by flip-flops |
In schematics, a small triangle > on the clock pin means edge-triggered. A small bubble (○) before it means negative edge.
3.5 Why edges instead of levels?
During a level, the inputs can change many times, and the output may follow them (unpredictable in feedback loops). An edge is an instant, so the circuit samples inputs at one well-defined moment. That makes the design predictable.
4. Synchronous vs Asynchronous Circuits
4.1 Synchronous sequential circuits
All memory elements are driven by one common clock. State changes happen only at clock edges.
Inputs ─► [Next-state logic] ─► [ FF ][ FF ][ FF ] ─► Outputs
▲ ▲ ▲ ▲
└──────────────────┴─┴─┘ (state feedback)
│
CLOCK (shared)
4.2 Asynchronous sequential circuits
There is no global clock. State changes happen whenever inputs change. Memory is typically built from latches / feedback loops with delays.
4.3 Comparison
| Aspect | Synchronous | Asynchronous |
|---|---|---|
| Clock | Common clock for all elements | No common clock |
| State changes | Only at clock edges | Any time inputs change |
| Design difficulty | Easier, well-structured | Harder, needs careful analysis |
| Timing analysis | Straightforward (setup/hold) | Complex |
| Hazards / races | Largely avoided by clock | Critical-race and hazard problems |
| Speed | Limited by clock period (worst-case path) | Can be faster (reacts immediately) |
| Power | Clock tree consumes power | Can be lower (no clock toggling) |
| Reliability | High, predictable | Prone to glitches if poorly designed |
| Examples | Counters, registers, CPUs | Ripple counters, latch-based handshake circuits |
4.4 Quick intuition
- Synchronous = a marching band, everyone steps on the beat.
- Asynchronous = a crowd, everyone moves the instant they get a cue.
4.5 Why most real designs are synchronous
The clock gives a safe window to settle: signals have an entire cycle to propagate and stabilise, and only then are they captured. This turns a messy analog-timing problem into a clean "does it meet the clock period?" question.
5. Timing Diagrams
5.1 What is a timing diagram?
A timing diagram shows how signals change over time, with time on the horizontal axis. It lets you see when things happen relative to the clock.
5.2 How to read one
- Each signal gets its own horizontal line (high = 1, low = 0).
- Vertical dotted lines usually mark clock edges.
- Buses (multi-bit signals) are shown as a pair of lines crossing at transitions, with the value written inside.
5.3 Example: positive-edge D flip-flop
t1 t2 t3 t4
│ │ │ │
CLK ┌──┐ │ ┌──┐ │ ┌──┐ │ ┌──┐
───┘ └─┼──┘ └─┼──┘ └─┼──┘ └──
↑ ↑ ↑ ↑ (rising edges)
D ____┌───────┐_______┌────────
____│ 1 │ 0 │ 1
Q ____________┌───────┐________
1 after t2 0 after t3
Observation: Q copies D only at the rising edge, and holds until the next one. Changes of D between edges are ignored.
5.4 What timing diagrams usually show
| Item | Meaning |
|---|---|
| Clock-to-Q delay | Small gap between the clock edge and Q changing |
| Setup window | Time before the edge that D must be stable |
| Hold window | Time after the edge that D must stay stable |
| Glitch | A short unwanted pulse on a signal |
5.5 Tips for drawing them
- Draw the clock first.
- Mark every active edge with a vertical guide line.
- For each edge, evaluate the inputs just before the edge, then update outputs just after it.
- Remember real outputs lag the edge by the propagation delay.
6. State Tables and State Diagrams
These are the two standard ways to describe the behaviour of a sequential circuit.
6.1 State diagram
A graph where:
- Circles (nodes) = states
- Arrows (edges) = transitions
- Labels on arrows = the input condition (and output, depending on model) causing the transition
6.2 State table
A table listing, for every present state and every input, the next state and the output.
6.3 Worked example: "detect two consecutive 1s"
A circuit has input X and output Z. Z = 1 when the last two inputs were 1, 1.
States
| State | Meaning |
|---|---|
A | Last input was 0 (or start) |
B | Last input was 1 (one 1 seen) |
State diagram (Mealy style, label = input / output)
0/0 0/0
┌─────┐ ┌─────────┐
▼ │ │ │
( A )───┘──── 1/0 ─────► ( B )◄──┐ │
▲ │ │ │1/1 │
└──────────── 0/0 ────────┘ └───┘ │
Simplified reading:
- From
A: input 0 → stay inA, output 0. Input 1 → go toB, output 0. - From
B: input 0 → go toA, output 0. Input 1 → stay inB, output 1.
State table
| Present State | Input X | Next State | Output Z |
|---|---|---|---|
| A | 0 | A | 0 |
| A | 1 | B | 0 |
| B | 0 | A | 0 |
| B | 1 | B | 1 |
6.4 Moore vs Mealy models
| Feature | Moore | Mealy |
|---|---|---|
| Output depends on | Present state only | Present state + current input |
| Output written on | The state (inside the circle) | The transition (on the arrow) |
| Number of states | Usually more | Usually fewer |
| Output timing | Changes only on clock edges (stable) | Can change when input changes (may glitch) |
| Response speed | Reacts one cycle later | Reacts faster |
6.5 State encoding
Each state is given a binary code stored in flip-flops. Number of flip-flops needed for N states:
n = ⌈ log₂ N ⌉
Example: 5 states → ⌈log₂ 5⌉ = 3 flip-flops.
6.6 From description to circuit (big picture)
- Understand the problem
- Draw the state diagram
- Build the state table
- Assign binary codes to states (state assignment)
- Derive next-state and output equations
- Draw the circuit using flip-flops and gates
7. Latches vs Flip-Flops
Both store one bit. The big difference is when they are allowed to change.
7.1 Latch (level-sensitive)
A latch is transparent while its enable/clock is at the active level: the output follows the input. When it goes inactive, the latch holds the last value.
SR Latch (basic building block)
Built from cross-coupled NOR gates (active-high inputs):
| S | R | Q (next) | Meaning |
|---|---|---|---|
| 0 | 0 | Q (no change) | Hold |
| 0 | 1 | 0 | Reset |
| 1 | 0 | 1 | Set |
| 1 | 1 | ✗ | Invalid / forbidden (both outputs forced to 0; unpredictable when released) |
(A NAND-based SR latch has active-low inputs, so its forbidden condition is S'=R'=0.)
Gated D Latch
Fixes the forbidden state by using a single data input D and an enable EN.
| EN | D | Q (next) |
|---|---|---|
| 0 | X | Q (hold) |
| 1 | 0 | 0 |
| 1 | 1 | 1 |
While EN = 1, Q follows D (transparent). When EN = 0, Q holds.
7.2 Flip-flop (edge-triggered)
A flip-flop samples its input only at a clock edge and holds the value for the whole cycle. It is commonly built from two latches in master-slave arrangement:
┌──────────┐ ┌──────────┐
D ──►│ MASTER │──────► │ SLAVE │──► Q
│ latch │ │ latch │
└────▲─────┘ └────▲─────┘
│ EN = CLK' │ EN = CLK
└────────CLK────────┘
- When CLK = 0: master is transparent (follows D), slave holds.
- When CLK = 1: master holds, slave becomes transparent (passes master's value).
- Net effect: output changes only at the rising edge.
D Flip-Flop truth table (positive-edge)
| CLK | D | Q (next) |
|---|---|---|
| ↑ | 0 | 0 |
| ↑ | 1 | 1 |
| Other (0, 1, ↓) | X | Q (hold) |
7.3 Latch vs Flip-Flop: the comparison
| Feature | Latch | Flip-Flop |
|---|---|---|
| Triggering | Level-sensitive | Edge-sensitive |
| Transparency | Transparent for the whole active level | Never transparent (samples at an instant) |
| Input changes during enable | Can propagate to output | Ignored except at the edge |
| Typical construction | Cross-coupled gates (+ gating) | Two latches (master + slave) |
| Gate count / area | Smaller | Larger |
| Power & speed | Lower power, can be faster | More robust but costlier |
| Timing analysis | Harder (time borrowing, races) | Easier, well defined |
| Common use | Building blocks, some custom low-power designs | Registers, counters, FSMs, most synchronous designs |
7.4 Why flip-flops dominate in synchronous design
A latch's transparency means that during the enable-active period, data can race through multiple stages. A flip-flop breaks that path every cycle, so each stage gets a clean, one-cycle-at-a-time hand-off.
7.5 Other common flip-flop types (for reference)
| Type | Behaviour in one line |
|---|---|
| D | Q⁺ = D (stores data) |
| T | Toggles when T = 1, holds when T = 0 (Q⁺ = T ⊕ Q) |
| JK | Set / Reset / Hold / Toggle; no forbidden state |
| SR (clocked) | Like SR latch but edge-triggered; S=R=1 still forbidden |
8. Setup Time, Hold Time and Propagation Delay
These three numbers decide whether a flip-flop captures data correctly and how fast a circuit can run.
8.1 Definitions
| Term | Symbol | Meaning |
|---|---|---|
| Setup time | t_su | Minimum time the data input D must be stable BEFORE the active clock edge |
| Hold time | t_h | Minimum time D must remain stable AFTER the active clock edge |
| Clock-to-Q (propagation) delay | t_cq (or t_pd) | Time from the clock edge until the output Q becomes valid |
| Combinational propagation delay | t_pd(comb) | Time for a signal to travel through the logic between flip-flops |
| Contamination (min) delay | t_cd | The shortest time before the output starts to change (fastest path) |
8.2 The "camera shutter" analogy
Think of the clock edge as a camera shutter:
- Setup time: the subject must be still just before the click.
- Hold time: the subject must stay still just after the click.
- If they move in that window, the photo (captured data) is blurry (wrong or unstable).
8.3 Visual
setup hold
◄────────►◄───────►
│
CLK ──────────────────┼┌──────────
││
rising edge
D ═══════════╗ │ ╔═════
(may change) ║ STABLE REQUIRED ║ (may change)
╚═══════╪═══════╝
│
Q │───►───┐
t_cq new Q valid
8.4 What happens if violated?
- Setup violation: data arrives too late → flip-flop may capture the old value or go metastable.
- Hold violation: data changes too soon after the edge → flip-flop may capture a wrong/corrupted value or go metastable.
8.5 Timing between two flip-flops
┌─────┐ ┌───────────────┐ ┌─────┐
│ FF1 ├───►│ Combinational ├───►│ FF2 │
└──▲──┘ │ Logic │ └──▲──┘
│ └───────────────┘ │
CLK CLK
Setup (max-delay) constraint → sets the maximum clock frequency
The data launched at FF1 must reach FF2 and settle before the next edge:
T_clk ≥ t_cq + t_pd(comb, max) + t_su
f_max = 1 / ( t_cq + t_pd(comb, max) + t_su )
Hold (min-delay) constraint → independent of clock frequency
The new data from FF1 must not arrive at FF2 too early (before FF2 finishes holding the old data):
t_cq(min) + t_cd(comb, min) ≥ t_h
Remember: fixing a setup violation = slow the clock down or shorten the logic. Fixing a hold violation = add delay to the short path. Slowing the clock does not fix hold.
8.6 Worked example
Given: t_cq = 2 ns, t_pd(comb) = 6 ns, t_su = 1 ns.
T_min = 2 + 6 + 1 = 9 ns
f_max = 1 / 9 ns ≈ 111 MHz
8.7 Setup vs Hold at a glance
| Setup | Hold | |
|---|---|---|
| Relative to clock edge | Before | After |
| Related path | Longest (worst-case) path | Shortest (best-case) path |
| Depends on clock period? | Yes | No |
| Fix | Reduce logic delay / slow clock | Add delay on the short path |
9. Clock Skew and Clock Jitter
In an ideal world, the clock reaches every flip-flop at the same instant, with perfect regularity. Real life is messier.
9.1 Clock skew
Definition: the difference in clock arrival time between two flip-flops in the same clock cycle.
CLK source
│
┌──────┴──────┐
(short wire) (long wire)
│ │
FF1 FF2
edge at t=0 edge at t=0 + skew
- Cause: different wire lengths, buffer delays, loads, process variations.
- Nature: mostly static / systematic: the same offset every cycle.
Effect on timing
Let t_skew = (clock arrival at capturing FF) − (clock arrival at launching FF).
| Skew direction | Setup | Hold |
|---|---|---|
| Positive (capture clock arrives later than launch) | Gets easier (more time) | Gets harder (risk of violation) |
| Negative (capture clock arrives earlier than launch) | Gets harder (less time) | Gets easier |
Modified constraints:
Setup: T_clk ≥ t_cq + t_pd(comb, max) + t_su − t_skew
Hold: t_cq(min) + t_cd(comb, min) ≥ t_h + t_skew
(with t_skew = capture arrival − launch arrival)
9.2 Clock jitter
Definition: the variation of a clock edge from its ideal position in time, so that the period is not perfectly constant.
Ideal: │ │ │ │ │
Actual: │ │ │ │ │
^ edges wobble around the ideal positions
- Cause: power-supply noise, thermal noise, crosstalk, PLL imperfections.
- Nature: random / dynamic: changes from cycle to cycle.
Common types of jitter
| Type | Meaning |
|---|---|
| Period jitter | Deviation of one period from the ideal period |
| Cycle-to-cycle jitter | Difference between two adjacent periods |
| Long-term (accumulated) jitter | Drift of an edge from ideal over many cycles |
Effect on timing
Jitter shrinks the usable clock period, because an edge might arrive earlier or later than expected. Designers include a jitter margin in the setup budget:
T_clk ≥ t_cq + t_pd(comb, max) + t_su + t_jitter (+ skew effects)
9.3 Skew vs Jitter
| Feature | Clock Skew | Clock Jitter |
|---|---|---|
| Compares | Different locations (two FFs), same cycle | Same location, different cycles (over time) |
| Nature | Spatial, mostly fixed | Temporal, random |
| Main causes | Routing and buffer differences | Noise, PLL / source imperfections |
| Can it help? | Sometimes (intentional "useful skew") | No, always a degradation |
| Impact | Shifts setup/hold margins | Reduces effective period / margins |
10. Metastability and Synchronizers
10.1 What is metastability?
A flip-flop is metastable when its output is stuck at an undefined voltage between 0 and 1 for an unpredictable amount of time before eventually resolving to a valid 0 or 1.
Analogy: a ball balanced on top of a hill. It will eventually roll to one side, but you can't tell which side, or when.
Energy
│ ▲ (metastable point, unstable equilibrium)
│ / \
│ / \
│ ___/ \___
│ (0) (1) ← two stable states
10.2 When does it happen?
Whenever the setup or hold time is violated, i.e., the input changes inside the forbidden window around the clock edge.
This is unavoidable when a signal is asynchronous to the clock domain that samples it, for example:
- A push-button pressed by a human
- A signal arriving from a different clock domain
- An external sensor input
Because such a signal can change at any moment, sooner or later it will change right at the clock edge.
10.3 Why is it dangerous?
- The output may sit at an invalid voltage level.
- Downstream gates may interpret that level differently (one sees 0, another sees 1), causing inconsistent behaviour and system failure.
- Output may arrive late, breaking the timing of the next stage.
10.4 Key facts
- You cannot eliminate metastability for asynchronous inputs. You can only reduce the probability of failure to an acceptably tiny level.
- The longer you wait after the clock edge, the more likely the flip-flop has resolved. The probability of staying metastable decays exponentially with time.
10.5 The synchronizer: the standard fix
A synchronizer gives a possibly-metastable signal extra time to settle before the rest of the circuit uses it.
Two-flip-flop synchronizer
┌──────┐ ┌──────┐
async_in ───►│ FF1 ├───────►│ FF2 ├───► sync_out
│ │ (may │ │ (safe to use)
└──▲───┘ be └──▲───┘
│ metastable) │
CLK (destination domain clock)
How it works:
- FF1 samples the asynchronous input. It might go metastable.
- It is given one full clock period to resolve.
- FF2 samples FF1's (now almost certainly stable) output.
- Everything after FF2 sees a clean, synchronised signal.
Things to remember
- Do not put logic between FF1 and FF2. Any logic delay eats up the settling time.
- Synchronizer flip-flops should be placed close together to minimise wire delay.
- Adds latency: typically 1 to 2 clock cycles of delay on the signal.
- A three-flip-flop synchronizer gives even more settling time for very high-frequency or high-reliability designs.
10.6 Reliability: MTBF
Reliability is measured by Mean Time Between Failures (MTBF), the average time between synchronizer failures.
MTBF = e^(t_r / τ) / ( T_0 · f_clk · f_data )
| Symbol | Meaning |
|---|---|
t_r | Resolution (settling) time available |
τ (tau) | Time constant of the flip-flop's metastability resolution (smaller = better) |
T_0 | Constant tied to the width of the vulnerable window |
f_clk | Sampling clock frequency |
f_data | Rate at which the asynchronous data changes |
Reading the formula:
- Larger
t_r→ MTBF grows exponentially (this is why a second flip-flop helps so much). - Higher
f_clkorf_data→ more chances to hit the window → MTBF drops.
10.7 Important limitations of a simple synchronizer
- It works well for single-bit signals.
- For a multi-bit bus crossing domains, bits may be sampled on different cycles and give an inconsistent value, so a plain two-flop per bit is not enough there.
- The input pulse must be long enough (generally at least one destination clock period) to be reliably captured.
10.8 Metastability summary table
| Question | Answer |
|---|---|
| What is it? | Flip-flop output stuck at an undefined level for an unpredictable time |
| Cause | Setup/hold violation, typically from asynchronous inputs |
| Can it be removed? | No, only made extremely unlikely |
| Standard solution | 2-FF (or 3-FF) synchronizer |
| Cost | 1 to 2 cycles of extra latency |
| Reliability metric | MTBF |
11. Quick Revision Cheat Sheet
Core ideas in one place
| Topic | Remember this |
|---|---|
| Combinational | Output = f(current inputs). No memory |
| Sequential | Output = f(current inputs, state). Has memory + feedback |
| State | The stored information; n flip-flops → up to 2ⁿ states |
| Clock | Periodic square wave; f = 1/T; edges are the "action moments" |
| Synchronous | One common clock, state changes at edges, easier and reliable |
| Asynchronous | No common clock, reacts to inputs directly, prone to hazards/races |
| Timing diagram | Signals vs time, used to verify behaviour cycle by cycle |
| State diagram / table | Graph / table describing present state, input → next state, output |
| Moore / Mealy | Output from state only / output from state + input |
| Latch | Level-sensitive, transparent while enabled |
| Flip-flop | Edge-triggered, samples at an instant (master + slave latches) |
| Setup time | Data stable before edge |
| Hold time | Data stable after edge |
| t_cq | Delay from clock edge to valid Q |
| Max frequency | T ≥ t_cq + t_pd(comb) + t_su |
| Clock skew | Same cycle, different places, arrival-time difference |
| Clock jitter | Same place, different cycles, edge-time variation |
| Metastability | Output stuck between 0 and 1 after a setup/hold violation |
| Synchronizer | 2-FF chain that gives time to resolve; no logic in between |
Common mistakes to avoid
- Saying a latch and a flip-flop are the same. A latch is level-sensitive; a flip-flop is edge-triggered.
- Thinking a lower clock frequency fixes hold violations. It doesn't; only setup depends on the period.
- Confusing skew (between two points) with jitter (variation over time).
- Putting combinational logic between synchronizer flip-flops.
- Forgetting that Moore outputs depend on state only.
- Assuming metastability can be fully eliminated. It can only be made very rare.
Likely quick-fire questions
- Why does a sequential circuit need feedback? To hold a state, i.e., to remember.
- Why are flip-flops preferred over latches in synchronous design? Edge-triggering gives a clean, predictable one-sample-per-cycle behaviour and simpler timing analysis.
- What limits the maximum clock frequency? Clock-to-Q + worst-case logic delay + setup time (adjusted for skew and jitter).
- Why use two flip-flops in a synchronizer? To give the first one a full clock period to resolve metastability before the value is used.
##Latches and Flip-Flops#
Study notes on the one-bit memory elements that every sequential circuit is built from. We start with the simplest cross-coupled latch and work up through every flip-flop type, the tables and equations that describe them, the classic race-around problem, master-slave fixes, conversions and real applications.
Table of Contents
- Big Picture: What Are We Building?
- SR Latch (NOR and NAND)
- Gated SR Latch
- D Latch
- SR Flip-Flop
- JK Flip-Flop
- D Flip-Flop
- T Flip-Flop
- Truth Tables vs Characteristic Tables
- Characteristic Equations
- Excitation Tables
- Race-Around Condition in JK Flip-Flops
- Master-Slave Flip-Flops
- Edge-Triggered vs Level-Triggered Devices
- Flip-Flop Conversion Techniques
- Applications of Flip-Flops
- Quick Revision Cheat Sheet
1. Big Picture: What Are We Building?
A latch or flip-flop is a bistable circuit: it has two stable states (Q = 0 or Q = 1) and can hold one bit indefinitely, as long as power is on.
The family tree of what we'll cover:
Basic SR latch (NOR / NAND)
│ add an enable (clock) input
▼
Gated SR latch ──── tie R = S' ────► D latch (all LEVEL-triggered)
│
│ make it EDGE-triggered (or master-slave)
▼
SR FF ─► JK FF (fixes invalid state) ─► T FF (J = K)
│
└─► D FF (single data input) (EDGE-triggered)
| Term | One-line meaning |
|---|---|
| Latch | Storage element whose output can change while the enable is active (level-sensitive) |
| Flip-flop | Storage element whose output changes only at a clock edge (edge-triggered), or pulse-triggered in master-slave form |
| Q | Stored bit (output) |
| Q' (Q̅) | Complement of the stored bit |
| Q (present) / Q⁺ (next) | Value before / after the clock event |
2. SR Latch (using NOR and NAND gates)
The SR latch (Set-Reset latch) is the most basic memory cell: two cross-coupled gates, where each gate's output feeds the other's input.
- S = Set (force Q to 1)
- R = Reset (force Q to 0)
2.1 SR latch using NOR gates (active-HIGH inputs)
┌─────────┐
R ─────┤ │
│ NOR ├──────┬───── Q
┌────┤ │ │
│ └─────────┘ │
│ │ (cross-coupled)
│ ┌─────────┐ │
└────┤ │ │
│ NOR ├──────┘
S ─────┤ │──────────── Q'
└─────────┘
Equations: Q = (R + Q')' and Q' = (S + Q)'
Truth table
| S | R | Q (next) | Q' (next) | Operation |
|---|---|---|---|---|
| 0 | 0 | Q (no change) | Q' | Hold / memory |
| 0 | 1 | 0 | 1 | Reset |
| 1 | 0 | 1 | 0 | Set |
| 1 | 1 | 0 | 0 | Invalid / forbidden |
Why S = R = 1 is a problem:
- Both outputs are forced to 0, so Q and Q' are no longer complements.
- If S and R return to 0 together, both gates race to flip; the final state is unpredictable.
2.2 SR latch using NAND gates (active-LOW inputs)
Here the inputs are S' and R' (active low). A 0 on an input triggers the action.
Truth table
| S' | R' | Q (next) | Q' (next) | Operation |
|---|---|---|---|---|
| 1 | 1 | Q (no change) | Q' | Hold / memory |
| 0 | 1 | 1 | 0 | Set |
| 1 | 0 | 0 | 1 | Reset |
| 0 | 0 | 1 | 1 | Invalid / forbidden |
2.3 NOR vs NAND latch at a glance
| Feature | NOR SR latch | NAND SR latch |
|---|---|---|
| Active input level | HIGH (1) | LOW (0) |
| Hold condition | S = R = 0 | S' = R' = 1 |
| Set | S = 1, R = 0 | S' = 0, R' = 1 |
| Reset | S = 0, R = 1 | S' = 1, R' = 0 |
| Forbidden | S = R = 1 (Q = Q' = 0) | S' = R' = 0 (Q = Q' = 1) |
2.4 Key points
- Output reacts immediately to input changes; there is no clock here (asynchronous).
- The forbidden input combination must be avoided by the user; the circuit does not protect itself.
3. Gated SR Latch
A gated SR latch adds an enable (EN) / clock (CLK) input so the latch only listens to S and R when permitted.
3.1 Construction (NAND version)
S ──┐
├─[NAND]──► S' ──┐
EN ─┤ ├─[NAND latch]──► Q
├─[NAND]──► R' ──┘ Q'
R ──┘
Two input NAND gates "gate" S and R with EN. Their outputs feed a basic NAND SR latch.
3.2 Truth table
| EN | S | R | Q (next) | Operation |
|---|---|---|---|---|
| 0 | X | X | Q | Hold (inputs ignored) |
| 1 | 0 | 0 | Q | Hold |
| 1 | 0 | 1 | 0 | Reset |
| 1 | 1 | 0 | 1 | Set |
| 1 | 1 | 1 | ✗ | Invalid |
3.3 Takeaways
- EN = 0: latch is "closed", inputs have no effect.
- EN = 1: latch is "open", behaves as a normal SR latch.
- It is level-triggered: while EN = 1, any change in S/R can change Q.
- It still has the S = R = 1 invalid state.
4. D Latch
The D latch (Data / Delay latch) removes the forbidden state by deriving R from S automatically, so only one data input D is needed.
4.1 Construction
Take the gated SR latch and connect:
S = D R = D'
So S and R are always opposite, and S = R = 1 can never occur.
D ───────────────┬─────► S
│ [Gated SR latch] ──► Q
D ──►[NOT]───────┴─────► R Q'
EN ───────────────────► EN
4.2 Truth table
| EN | D | Q (next) | Operation |
|---|---|---|---|
| 0 | X | Q | Hold |
| 1 | 0 | 0 | Reset (Q follows D) |
| 1 | 1 | 1 | Set (Q follows D) |
4.3 Characteristic equation
Q⁺ = D (when EN = 1)
Q⁺ = Q (when EN = 0)
4.4 Transparency
When EN = 1 the latch is transparent: Q simply follows D, like an open window. When EN = 0, the latch is opaque: it holds the last value D had at the moment EN fell.
EN ───┐ ┌────────┐ ┌───
└────────┘ └────────┘
D ─┐ ┌─┐ ┌──┐ ┌─┐ ┌────
└──┘ └───┘ └──┘ └───┘
Q ─┐ ┌─┐ ┌──┐ (holds) ┌──
└──┘ └───┘ ... (follows D only while EN = 1)
Drawback: if D changes during EN = 1, the change races through to Q. That uncertainty is why we need edge-triggered flip-flops (Section 14).
5. SR Flip-Flop
A clocked SR flip-flop behaves like the gated SR latch, but it responds only at the clock edge (or via master-slave), not during the whole level.
5.1 Symbol
┌────────┐
S ───┤ ├─── Q
│ SR │
CLK ───┤> │
│ FF │
R ───┤ ├─── Q'
└────────┘
The small > triangle = edge-triggered clock input.
5.2 Truth table (positive-edge)
| CLK | S | R | Q⁺ | Operation |
|---|---|---|---|---|
| ↑ | 0 | 0 | Q | No change |
| ↑ | 0 | 1 | 0 | Reset |
| ↑ | 1 | 0 | 1 | Set |
| ↑ | 1 | 1 | ? | Invalid (avoid) |
Limitation: the S = R = 1 combination is still not allowed. This is exactly what the JK flip-flop fixes.
6. JK Flip-Flop
The JK flip-flop is the "universal" flip-flop. It works like an SR flip-flop (J = Set, K = Reset) but uses the S = R = 1 case for something useful: toggle.
6.1 Symbol
┌────────┐
J ───┤ ├─── Q
│ JK │
CLK ───┤> │
│ FF │
K ───┤ ├─── Q'
└────────┘
6.2 Truth table
| J | K | Q⁺ | Operation |
|---|---|---|---|
| 0 | 0 | Q | No change (hold) |
| 0 | 1 | 0 | Reset |
| 1 | 0 | 1 | Set |
| 1 | 1 | Q' | Toggle (complement) |
6.3 Internal idea
A JK flip-flop is an SR flip-flop with feedback from the outputs into the input gates:
S = J · Q'
R = K · Q
Because Q and Q' are always opposite, S and R can never both be 1 at the same time. The invalid state is therefore eliminated.
6.4 Why "toggle" matters
With J = K = 1, every clock edge flips the output: 0 → 1 → 0 → 1 ... This gives a divide-by-2 behaviour, which is the basis of counters.
7. D Flip-Flop
The D flip-flop (Data / Delay FF) copies its input D to the output on the active clock edge.
7.1 Symbol
┌────────┐
D ───┤ ├─── Q
│ D │
CLK ───┤> │
│ FF │
│ ├─── Q'
└────────┘
7.2 Truth table
| D | Q⁺ | Operation |
|---|---|---|
| 0 | 0 | Reset |
| 1 | 1 | Set |
(Evaluated at the active clock edge; otherwise Q holds.)
7.3 Construction idea
A D flip-flop is an SR (or JK) flip-flop with the inputs forced to be complements:
From SR: S = D, R = D'
From JK: J = D, K = D'
7.4 Why it's so popular
- Only one data input, simplest to use.
- No invalid state, no toggle ambiguity.
- Behaves as a 1-cycle delay element: output at cycle n + 1 equals input at cycle n.
- Building block for registers and shift registers.
8. T Flip-Flop
The T flip-flop (Toggle FF) either holds or toggles, depending on T.
8.1 Symbol
┌────────┐
T ───┤ ├─── Q
│ T │
CLK ───┤> │
│ FF │
│ ├─── Q'
└────────┘
8.2 Truth table
| T | Q⁺ | Operation |
|---|---|---|
| 0 | Q | No change |
| 1 | Q' | Toggle |
8.3 Construction idea
- From JK: tie J and K together →
J = K = T. - From D: feed
D = T ⊕ Q.
8.4 Frequency division
With T = 1, Q toggles on every active edge, so Q's frequency is half of CLK. Chain n of these, and you get a divide-by-2ⁿ.
CLK ─┐ ┌─┐ ┌─┐ ┌─┐ ┌─┐ ┌─┐ ┌─┐ ┌─┐ ┌─
└─┘ └─┘ └─┘ └─┘ └─┘ └─┘ └─┘ └─┘
Q ──┐ ┌─────┐ ┌─────┐ ┌──
└─────┘ └─────┘ └─────┘ (period = 2 × CLK period)
9. Truth Tables and Characteristic Tables
These are two ways to describe a flip-flop. They look similar but answer different questions.
| Table | Question it answers | Format |
|---|---|---|
| Truth table (function table) | "If I apply these inputs, what happens?" | Inputs → action / next state |
| Characteristic table | "Given the present output Q and the inputs, what is the next output Q⁺?" | Inputs + present state Q → Q⁺ |
The characteristic table is the one used for analysis (what does this FF do?).
9.1 Characteristic tables
SR flip-flop
| S | R | Q | Q⁺ |
|---|---|---|---|
| 0 | 0 | 0 | 0 |
| 0 | 0 | 1 | 1 |
| 0 | 1 | 0 | 0 |
| 0 | 1 | 1 | 0 |
| 1 | 0 | 0 | 1 |
| 1 | 0 | 1 | 1 |
| 1 | 1 | 0 | X (invalid) |
| 1 | 1 | 1 | X (invalid) |
JK flip-flop
| J | K | Q | Q⁺ |
|---|---|---|---|
| 0 | 0 | 0 | 0 |
| 0 | 0 | 1 | 1 |
| 0 | 1 | 0 | 0 |
| 0 | 1 | 1 | 0 |
| 1 | 0 | 0 | 1 |
| 1 | 0 | 1 | 1 |
| 1 | 1 | 0 | 1 |
| 1 | 1 | 1 | 0 |
D flip-flop
| D | Q | Q⁺ |
|---|---|---|
| 0 | 0 | 0 |
| 0 | 1 | 0 |
| 1 | 0 | 1 |
| 1 | 1 | 1 |
T flip-flop
| T | Q | Q⁺ |
|---|---|---|
| 0 | 0 | 0 |
| 0 | 1 | 1 |
| 1 | 0 | 1 |
| 1 | 1 | 0 |
10. Characteristic Equations
A characteristic equation is the characteristic table turned into a Boolean expression (usually via a K-map). It gives Q⁺ as a function of the inputs and Q.
| Flip-Flop | Characteristic equation | Notes |
|---|---|---|
| SR | Q⁺ = S + R'Q | Subject to the constraint S·R = 0 |
| JK | Q⁺ = JQ' + K'Q | No constraint |
| D | Q⁺ = D | Output copies input |
| T | Q⁺ = T ⊕ Q = TQ' + T'Q | Toggles when T = 1 |
10.1 Quick derivation: JK
From the JK characteristic table, Q⁺ = 1 for exactly these four (J, K, Q) combinations:
J=1, K=0, Q=0 → 1J=1, K=0, Q=1 → 1J=1, K=1, Q=0 → 1J=0, K=0, Q=1 → 1
K-map simplification gives:
Q⁺ = J·Q' + K'·Q
Sanity check: J = K = 1 gives Q' + 0 = Q', a toggle. ✓
10.2 Quick derivation: T
T flip-flop = JK with J = K = T. Substituting: Q⁺ = TQ' + T'Q = T ⊕ Q. ✓
11. Excitation Tables
A characteristic table says: given inputs, what's the next state? An excitation table says the reverse: to go from present state Q to desired next state Q⁺, what inputs are needed?
This is the table used for design (and for flip-flop conversion, counters, and state machines).
11.1 Excitation tables of all four flip-flops
| Q | Q⁺ | SR: S | R | JK: J | K | D: D | T: T |
|---|---|---|---|---|---|---|---|
| 0 | 0 | 0 | X | 0 | X | 0 | 0 |
| 0 | 1 | 1 | 0 | 1 | X | 1 | 1 |
| 1 | 0 | 0 | 1 | X | 1 | 0 | 1 |
| 1 | 1 | X | 0 | X | 0 | 1 | 0 |
(X = don't care)
11.2 How to read it
Take the SR flip-flop, transition 0 → 1:
- Only Set does this →
S = 1, R = 0.
Take the JK flip-flop, transition 0 → 1:
- Either Set (J=1, K=0) or Toggle (J=1, K=1) works →
J = 1, K is don't care.
Those "don't cares" are what make JK-based designs simpler.
11.3 Memory trick
- D: the input is simply the desired next state (
D = Q⁺). - T: the input is 1 whenever the state must change (
T = Q ⊕ Q⁺).
12. Race-Around Condition in JK Flip-Flops
12.1 What is it?
When J = K = 1 the JK flip-flop must toggle once per clock. But if the flip-flop is level-triggered and the clock pulse stays HIGH longer than the propagation delay of the flip-flop, the output toggles again and again during that single pulse. The final value becomes uncertain. This is the race-around condition.
12.2 Step-by-step
- CLK goes HIGH with J = K = 1, and Q = 0.
- After propagation delay Δt, Q becomes 1.
- This new Q is fed back, and CLK is still HIGH, so the flip-flop sees J = K = 1 again → toggles to 0.
- After another Δt, Q becomes 0 → toggles to 1 ... and so on until CLK falls.
CLK ┌────────────────────────┐
│ │
────┘ └────
Q ┌──┐ ┌──┐ ┌──┐ ┌──┐
────┘ └──┘ └──┘ └──┘ └──── (multiple toggles in ONE clock pulse)
Δt
If the pulse width is t_p then roughly t_p / Δt toggles occur, so the final state depends on whether that number is odd or even, i.e. effectively unpredictable.
12.3 Condition for it to occur
J = K = 1 and t_p > Δt (level-triggered clock)
12.4 How to avoid it
| Solution | How it helps |
|---|---|
| Edge triggering | Flip-flop looks at the inputs only at one instant; feedback during the rest of the pulse is ignored |
| Master-slave configuration | Output change is separated from input sampling, so the new Q cannot reach the input stage in the same pulse |
Narrow clock pulse (t_p < Δt) | Pulse ends before the output can change and feed back. Hard to guarantee in practice |
The standard, practical answer is master-slave or edge-triggered flip-flops.
13. Master-Slave Flip-Flops
13.1 The idea
Use two latches back to back:
- Master: takes in the inputs.
- Slave: drives the final output.
They are enabled on opposite clock levels, so they are never transparent at the same time. That isolates the output from the input and kills the race-around problem.
13.2 Master-slave JK flip-flop
┌────────────┐ ┌────────────┐
J ────────►│ │ │ │
│ MASTER ├─ Qm ────►│ SLAVE ├──── Q
K ────────►│ gated SR │ │ gated SR │
│ ├─ Qm' ───►│ ├──── Q'
└─────▲──────┘ └─────▲──────┘
│ EN = CLK │ EN = CLK'
│ │
CLK ─────────────┴───────[NOT]───────────┘
Feedback: Q' ──► master's J-side gate, Q ──► master's K-side gate
13.3 Operation (classic version)
| Clock level | Master | Slave | What happens |
|---|---|---|---|
| HIGH (1) | Enabled (transparent), captures J, K | Disabled (holds) | Inputs are sampled into the master; Q does not change |
| HIGH → LOW (falling edge) | Closes | Opens | Master's value is passed to the slave → Q updates |
| LOW (0) | Disabled (holds) | Enabled, follows master | Master ignores any input changes |
So the output changes at the trailing (falling) edge of the clock pulse. This is why it is sometimes called pulse-triggered.
(If the master is enabled by CLK' and the slave by CLK, the output instead changes on the rising edge.)
13.4 Why race-around disappears
The feedback signals Q and Q' come from the slave, which is disabled during the whole HIGH period of the clock. They cannot change while the master is listening. So the master sees stable feedback and only one toggle happens per clock cycle.
13.5 Master-slave D flip-flop
Same structure: a D latch (master) followed by a D latch (slave) with opposite enables.
13.6 Limitation: "1s catching" / "0s catching"
Because the master is level-sensitive during the active clock period, a short unwanted glitch on J or K while the clock is HIGH can be captured by the master and then passed on, even if the inputs return to normal before the falling edge. This is why the truly edge-triggered design is often preferred for noisy inputs.
14. Edge-Triggered vs Level-Triggered Devices
14.1 Definitions
- Level-triggered: responds during the entire time the clock (enable) is at its active level (HIGH or LOW). Examples: SR latch (gated), D latch.
- Edge-triggered: responds only at the instant of a clock transition: rising (positive) or falling (negative) edge. Examples: edge-triggered D, JK, T flip-flops.
14.2 Symbols
Level-triggered (active high) Positive-edge-triggered Negative-edge-triggered
┌────────┐ ┌────────┐ ┌────────┐
CLK ─┤ EN │ CLK ─┤> │ CLK ─○> │
└────────┘ └────────┘ └────────┘
(no triangle) (triangle) (triangle + bubble)
14.3 Waveform comparison
CLK ┌───────┐ ┌───────┐
───┘ └───────┘ └───
↑ ↓ ↑ ↓
rising falling
Level (high) : active ────────── active ─────── (whole HIGH period)
Pos-edge : active ↑ (instant) active ↑ (instant)
Neg-edge : active ↓ (instant) active ↓ (instant)
14.4 Comparison table
| Feature | Level-triggered | Edge-triggered |
|---|---|---|
| Responds to | The level (HIGH/LOW) of clock | The transition (edge) of clock |
| Active window | Long (entire pulse width) | Extremely short (an instant) |
| Input changes during active period | Affect the output | Ignored (only value at edge matters) |
| Transparent? | Yes, while enabled | No |
| Race-around risk (JK) | Yes | No |
| Noise / glitch sensitivity | High | Low |
| Typical devices | Latches | Flip-flops |
| Timing predictability | Harder | Easier |
14.5 Takeaway
Edge-triggering gives one clean sample per clock cycle, which is why flip-flops, not latches, are the default building block for registers, counters and state machines.
15. Flip-Flop Conversion Techniques
15.1 Why convert?
You may need a T flip-flop but only have JK flip-flops on hand (or need a D FF from JK, and so on). Conversion means building flip-flop X using flip-flop Y plus some extra gates.
15.2 General procedure (the 5-step method)
Suppose you want to build flip-flop X (target) using flip-flop Y (available):
- Write the characteristic table of X (target): inputs of X, present state Q, next state Q⁺.
- Write the excitation table of Y (available) for each Q → Q⁺ transition in that table.
- Fill in the inputs of Y required for each row.
- Simplify each input of Y as a Boolean function of (X's inputs, Q) using K-maps.
- Draw the circuit: X's inputs go through the derived logic into Y's inputs, with Y's clock shared.
X inputs ─►[ Conversion logic ]─► Y inputs ─►[ Flip-flop Y ]─► Q, Q'
▲ │
└────────── Q (feedback) ────────┘
CLK ──────────────► (to Y)
15.3 Worked example: Convert JK → T
Step 1: characteristic table of T
| T | Q | Q⁺ |
|---|---|---|
| 0 | 0 | 0 |
| 0 | 1 | 1 |
| 1 | 0 | 1 |
| 1 | 1 | 0 |
Step 2 and 3: JK inputs needed (from the JK excitation table)
| T | Q | Q⁺ | J | K |
|---|---|---|---|---|
| 0 | 0 | 0 | 0 | X |
| 0 | 1 | 1 | X | 0 |
| 1 | 0 | 1 | 1 | X |
| 1 | 1 | 0 | X | 1 |
Step 4: K-maps
J: 1 in the row (T=1, Q=0), X in (T=0,Q=1) and (T=1,Q=1) →J = TK: 1 in the row (T=1, Q=1), X in (T=0,Q=0) and (T=1,Q=0) →K = T
Step 5: circuit: simply connect J and K together to T.
T ──┬──► J ┐
│ │ JK FF ──► Q
└──► K ┘
CLK ──────►
15.4 Worked example: Convert SR → D
| D | Q | Q⁺ | S | R |
|---|---|---|---|---|
| 0 | 0 | 0 | 0 | X |
| 0 | 1 | 0 | 0 | 1 |
| 1 | 0 | 1 | 1 | 0 |
| 1 | 1 | 1 | X | 0 |
Simplifying: S = D and R = D'. (A NOT gate on D.)
15.5 Summary of common conversions
| Convert (target ← available) | Input equations |
|---|---|
| SR → D | S = D, R = D' |
| SR → T | S = T·Q', R = T·Q |
| SR → JK | S = J·Q', R = K·Q |
| JK → D | J = D, K = D' |
| JK → T | J = K = T |
| JK → SR | J = S, K = R (with S·R = 0 assumed) |
| D → T | D = T ⊕ Q |
| D → JK | D = J·Q' + K'·Q |
| D → SR | D = S + R'·Q |
| T → D | T = D ⊕ Q |
| T → JK | T = J·Q' + K·Q |
| T → SR | T = S·Q' + R·Q |
15.6 Shortcut to remember
The input equation for a D flip-flop is simply the characteristic equation of the target flip-flop (since Q⁺ = D). And for a T flip-flop it is T = Q ⊕ Q⁺.
16. Applications of Flip-Flops
Flip-flops are the atoms of digital memory and sequencing. Almost everything that "remembers" or "counts" uses them.
16.1 Data storage: registers
- One flip-flop stores 1 bit; n flip-flops sharing a clock form an n-bit register.
- Used in CPUs for accumulators, instruction registers, and general-purpose registers.
D3 ─►[FF]─► Q3
D2 ─►[FF]─► Q2 (all share one CLK → loads all bits together)
D1 ─►[FF]─► Q1
D0 ─►[FF]─► Q0
16.2 Shift registers
- Flip-flops chained so each Q feeds the next D.
- On every clock, bits shift one position.
- Uses: serial-to-parallel and parallel-to-serial conversion, delay lines, simple data transfer.
16.3 Counters
- T or JK flip-flops (J = K = 1) toggle to build binary counters.
- Asynchronous (ripple) counters: each FF is clocked by the previous one.
- Synchronous counters: all FFs share one clock.
- Uses: timers, event counting, address generation, digital clocks.
16.4 Frequency division
- A T flip-flop (T = 1) halves the clock frequency.
- A chain of n flip-flops divides by 2ⁿ.
16.5 Memory cells
- Latch / flip-flop style cells are the basis of static RAM (SRAM) bits and register files.
16.6 State storage in sequential circuits / FSMs
- The flip-flops hold the present state; next-state logic computes the next state; the clock updates all flip-flops together.
- Uses: traffic-light controllers, vending machines, sequence detectors, control units.
16.7 Switch debouncing
- A mechanical switch "bounces" and produces several rapid pulses.
- An SR latch (NAND type) captures the first valid contact and ignores the later bounces, giving a clean single transition.
16.8 Synchronizing signals
- A D flip-flop samples an input at a clock edge and aligns it with the system clock, so downstream logic sees a clean, clock-aligned signal.
16.9 Applications summary
| Application | Flip-flop commonly used | Role |
|---|---|---|
| Registers | D | Store multi-bit data |
| Shift registers | D (or JK) | Move/shift bits serially |
| Counters | T / JK | Toggle to count |
| Frequency dividers | T | Divide by 2 per stage |
| Switch debouncing | SR latch | Hold first valid transition |
| State machines | D / JK | Store present state |
| Memory cells | Latch-based | Store 1 bit per cell |
17. Quick Revision Cheat Sheet
Characteristic equations
| FF | Equation |
|---|---|
| SR | Q⁺ = S + R'Q (S·R = 0) |
| JK | Q⁺ = JQ' + K'Q |
| D | Q⁺ = D |
| T | Q⁺ = T ⊕ Q |
Excitation table
| Q → Q⁺ | S R | J K | D | T |
|---|---|---|---|---|
| 0 → 0 | 0 X | 0 X | 0 | 0 |
| 0 → 1 | 1 0 | 1 X | 1 | 1 |
| 1 → 0 | 0 1 | X 1 | 0 | 1 |
| 1 → 1 | X 0 | X 0 | 1 | 0 |
One-liners to remember
| Topic | Remember this |
|---|---|
| NOR SR latch | Active-HIGH; forbidden at S = R = 1 |
| NAND SR latch | Active-LOW; forbidden at S' = R' = 0 |
| Gated SR latch | SR latch + enable; level-triggered |
| D latch | Gated SR with S = D, R = D'; transparent when EN = 1 |
| SR FF | Edge-triggered SR; S = R = 1 invalid |
| JK FF | SR with no invalid state; J = K = 1 toggles |
| D FF | Copies D at the edge; 1-cycle delay |
| T FF | Toggles when T = 1; divide-by-2 |
| Race-around | JK with J = K = 1, level-triggered, pulse width > propagation delay |
| Fix | Master-slave or edge triggering |
| Master-slave | Master (CLK high) + slave (CLK low); output changes at the falling edge |
| Conversion | Target's characteristic table + available FF's excitation table → K-map |
Common mistakes to avoid
- Mixing up characteristic tables (inputs + Q → Q⁺) with excitation tables (Q → Q⁺ → required inputs).
- Forgetting that the NAND SR latch is active-low, so its set/reset conditions are reversed from the NOR version.
- Thinking race-around happens in edge-triggered flip-flops. It only affects level-triggered JK with J = K = 1.
- Using
S = R = 1in an SR latch or SR flip-flop. - Forgetting the don't-care (X) entries while simplifying conversion K-maps.
- Treating a master-slave flip-flop as a latch. It is not transparent, and its output changes only at the clock transition.
Likely quick-fire questions
- Why is S = R = 1 forbidden in an SR latch? Both outputs go to the same level (Q = Q'), and the final state is unpredictable when the inputs are released together.
- How does a JK flip-flop avoid that problem? Feedback from Q and Q' guarantees S and R can't both be 1.
- What causes race-around? Level-triggered JK, J = K = 1, and clock pulse longer than propagation delay.
- How does master-slave solve it? The slave, which supplies the feedback, is disabled while the master is listening.
- Which flip-flop's input equals the next state directly? The D flip-flop (
D = Q⁺).
##Registers and Shift Registers#
Study notes on how flip-flops are grouped to store and move multi-bit data. We start with the idea of a register, then walk through every shift-register flavour (SISO, SIPO, PISO, PIPO), the bidirectional and universal versions, how to read their timing diagrams, the ring and Johnson variants, and finally where all of this is used.
Table of Contents
- Register Fundamentals
- Parallel Registers
- Shift Register Basics
- Serial-In Serial-Out (SISO)
- Serial-In Parallel-Out (SIPO)
- Parallel-In Serial-Out (PISO)
- Parallel-In Parallel-Out (PIPO)
- Bidirectional Shift Registers
- Universal Shift Registers
- Shift-Register Timing Diagrams
- Ring and Johnson Registers
- Applications in Data Storage and Transfer
- Quick Revision Cheat Sheet
1. Register Fundamentals
1.1 What is a register?
A register is a group of flip-flops that share a common clock and are used to store a multi-bit binary word.
- One flip-flop stores 1 bit.
- n flip-flops form an n-bit register, which can store 2ⁿ different values (one at a time).
Analogy: one flip-flop is a single mailbox slot holding a 0 or a 1. A register is a row of slots that together hold a whole number like 1011.
1.2 Two jobs a register can do
| Job | Meaning | Register type |
|---|---|---|
| Store data | Hold a word until it is replaced | Basic (parallel) register |
| Shift data | Move the stored bits one position per clock | Shift register |
1.3 Basic building blocks
- D flip-flops are the usual choice, because
Q⁺ = Dmakes loading trivial. - A common clock makes all bits update together.
- Optional control inputs:
| Control | Purpose |
|---|---|
| Clear / Reset | Force all bits to 0 (often asynchronous) |
| Load / Enable | Decide whether the register accepts new data or keeps its old value |
| Shift / Mode | Select the shifting behaviour (in shift registers) |
1.4 Serial vs parallel data
| Serial | Parallel | |
|---|---|---|
| How bits move | One bit at a time on a single line | All bits together, one line per bit |
| Wires needed | Few (1 data line) | Many (n data lines) |
| Speed per word | Slower (n clocks) | Faster (1 clock) |
| Typical use | Long-distance / low-pin-count links | Inside a processor, short-distance buses |
1.5 Four data-movement modes (preview)
OUTPUT
Serial Parallel
INPUT Serial SISO SIPO
Parallel PISO PIPO
2. Parallel Registers
2.1 Basic parallel register
The simplest register: n D flip-flops, one common clock, each bit loaded straight from its own input.
I3 ──►[D FF ]──► Q3
I2 ──►[D FF ]──► Q2
I1 ──►[D FF ]──► Q1
I0 ──►[D FF ]──► Q0
▲
CLK ─────┴─ (shared by all four)
Behaviour: on every active clock edge, Q3 Q2 Q1 Q0 ← I3 I2 I1 I0.
The problem: it reloads every clock. In practice we want to hold a value across many clocks and load only when told to.
2.2 Register with load control
Add a LOAD input and a 2:1 multiplexer in front of each D input:
D_i = LOAD · I_i + LOAD' · Q_i
┌─────┐
I_i ────►│ 1 │
│ MUX ├──► D ─►[FF]──► Q_i
Q_i ──┬─►│ 0 │ ▲
│ └──▲──┘ │
│ │ LOAD CLK
└─────┼──────────────┘ (Q fed back to hold)
| LOAD | Action at clock edge |
|---|---|
| 0 | Hold: each bit reloads its own Q (no change) |
| 1 | Load: Q ← I (new data enters) |
(Another approach is to gate the clock itself. The mux method is preferred because it keeps all flip-flops on the same clean clock.)
2.3 Register with clear
- Asynchronous clear: a CLEAR input resets all Q to 0 immediately, independent of the clock.
- Synchronous clear: the reset is applied through the data path, so it takes effect at the next clock edge.
2.4 Parallel register summary
| Feature | Detail |
|---|---|
| Storage element | D flip-flop per bit |
| Data in | All bits at once |
| Data out | All bits at once |
| Time to load a word | 1 clock cycle |
| Hold capability | Via load-control multiplexer |
3. Shift Register Basics
3.1 What is a shift register?
A shift register is a register whose flip-flops are chained so that, on each clock pulse, every bit moves one position along the chain.
Serial ┌─────┐ ┌─────┐ ┌─────┐ ┌─────┐
IN ─────►│ FF0 ├──►│ FF1 ├──►│ FF2 ├──►│ FF3 ├────► Serial OUT
└──▲──┘ └──▲──┘ └──▲──┘ └──▲──┘
└─────────┴─────────┴─────────┘
CLK
The Q of each flip-flop feeds the D of the next.
3.2 Why it works (the "simultaneous update" idea)
All flip-flops are edge-triggered and sample their D inputs at the same instant. So at the clock edge, each flip-flop captures the old value of its neighbour, and only afterwards does the output change. Bits therefore move exactly one step instead of rushing through the whole chain.
3.3 Shift direction
| Direction | Meaning |
|---|---|
| Shift right | Data moves from FF0 → FF1 → FF2 → FF3 (in these notes, serial input enters at FF0) |
| Shift left | Data moves the opposite way |
3.4 Naming convention for the four types
The name is (how data goes in) - (how data comes out): Serial or Parallel for each side.
4. Serial-In Serial-Out (SISO)
4.1 Structure
A plain chain of D flip-flops. Data enters one bit per clock at the first flip-flop and leaves one bit per clock from the last.
Din ─►[FF0]─►[FF1]─►[FF2]─►[FF3]─► Dout
▲ ▲ ▲ ▲
CLK ─────┴──────┴──────┴──────┘
4.2 Worked example: shifting in 1 0 1 1
Bits arrive in the order 1, 0, 1, 1 (first bit first). Register starts at Q0 Q1 Q2 Q3 = 0000.
| Clock | Din | Q0 | Q1 | Q2 | Q3 (Dout) | Comment |
|---|---|---|---|---|---|---|
| start | 0 | 0 | 0 | 0 | Cleared | |
| 1 | 1 | 1 | 0 | 0 | 0 | First bit enters |
| 2 | 0 | 0 | 1 | 0 | 0 | |
| 3 | 1 | 1 | 0 | 1 | 0 | |
| 4 | 1 | 1 | 1 | 0 | 1 | First bit reaches Q3 |
| 5 | 0 | 0 | 1 | 1 | 0 | 2nd bit leaves |
| 6 | 0 | 0 | 0 | 1 | 1 | 3rd bit leaves |
| 7 | 0 | 0 | 0 | 0 | 1 | 4th bit leaves |
The output stream at Q3 is 1, 0, 1, 1, the same sequence, delayed.
4.3 Key properties
- Delay line: an n-bit SISO delays data by n clock cycles.
- To load and fully unload an n-bit word takes about 2n − 1 clocks.
- Only one input pin and one output pin, so it needs very few connections.
- Data in the middle is not accessible (only the final output is available).
5. Serial-In Parallel-Out (SIPO)
5.1 Structure
Same chain as SISO, but every flip-flop output is brought out as a pin. Data goes in serially; once enough clocks have passed, the whole word is read at once.
Din ─►[FF0]─►[FF1]─►[FF2]─►[FF3]
│ │ │ │
Q0 Q1 Q2 Q3 ← read all together
5.2 Operation
After n clocks, the n bits that were shifted in are sitting in the n flip-flops. Using the same input stream 1 0 1 1, after clock 4 the register holds:
Q0 Q1 Q2 Q3 = 1 1 0 1
(The first bit sent ended up in Q3, the last bit sent is in Q0.) The parallel outputs are valid and can be sampled together at that moment. They are usually read after the n-th clock and before the next one.
5.3 Notes
- Main job: serial-to-parallel conversion.
- Outputs change on every clock while new data keeps shifting, so a downstream circuit must read them at the right time (or use an extra output latch to hold the word).
- Needs n clock pulses per word.
6. Parallel-In Serial-Out (PISO)
6.1 Structure
A shift register in which each flip-flop can either receive its own parallel input bit or take the bit from its left neighbour. A SHIFT / LOAD' control chooses which, using a 2:1 mux (or AND-OR gating) at each D input.
P0 P1 P2 P3
│ │ │ │
┌──▼──┐ ┌──▼──┐ ┌──▼──┐ ┌──▼──┐
SI(0) ─►│MUX ├FF0─►│MUX ├FF1─►│MUX ├FF2─►│MUX ├FF3──► Serial OUT
└──▲──┘ └──▲──┘ └──▲──┘ └──▲──┘
└──────────┴──────────┴──────────┘
SHIFT / LOAD'
Per-bit equation:
D_i = SHIFT' · P_i + SHIFT · Q_(i-1)
| SHIFT / LOAD' | Action at clock edge |
|---|---|
| 0 | Parallel load: Q_i ← P_i |
| 1 | Shift: Q_i ← Q_(i-1) |
6.2 Worked example: send P0 P1 P2 P3 = 1 0 1 1
- Load (SHIFT/LOAD' = 0, one clock):
Q0 Q1 Q2 Q3 = 1 0 1 1 - Shift (SHIFT/LOAD' = 1), serial out is taken from Q3:
| State | Q0 | Q1 | Q2 | Q3 (Out) |
|---|---|---|---|---|
| After load | 1 | 0 | 1 | 1 |
| Shift 1 | 0 | 1 | 0 | 1 |
| Shift 2 | 0 | 0 | 1 | 0 |
| Shift 3 | 0 | 0 | 0 | 1 |
The serial stream seen at Q3 is 1, 1, 0, 1, i.e. P3, P2, P1, P0 (the last bit goes out first in this arrangement).
6.3 Notes
- Main job: parallel-to-serial conversion.
- Takes 1 clock to load + n − 1 more clocks to push out the rest of the bits.
- Lets a wide bus be sent over a single wire.
7. Parallel-In Parallel-Out (PIPO)
7.1 Structure
All bits are loaded together and read together. It is the parallel register of Section 2: no bit-to-bit shifting is needed.
P3 P2 P1 P0
│ │ │ │
[D][D][D][D] ← common CLK
│ │ │ │
Q3 Q2 Q1 Q0
7.2 Notes
- Fastest type: 1 clock to load, outputs valid right after the edge.
- Needs many pins (n in + n out).
- Used purely for storage and buffering.
- Strictly speaking it doesn't "shift", so it's the simplest member of the family. (Universal shift registers, Section 9, add shifting on top of this.)
7.3 Comparison of the four basic types
| Type | Input | Output | Clocks to load a word | Clocks to read a word | Main use |
|---|---|---|---|---|---|
| SISO | Serial | Serial | n | n | Delay line, serial buffering |
| SIPO | Serial | Parallel | n | 1 (all at once) | Serial → parallel conversion |
| PISO | Parallel | Serial | 1 | n | Parallel → serial conversion |
| PIPO | Parallel | Parallel | 1 | 1 (all at once) | Temporary storage / buffer |
8. Bidirectional Shift Registers
8.1 Idea
A bidirectional shift register can shift right or left, chosen by a direction control input.
8.2 How it's built
Put a 2:1 multiplexer at each flip-flop's D input to choose between the left neighbour and the right neighbour:
D_i = RIGHT · Q_(i-1) + RIGHT' · Q_(i+1)
Q(i-1) ─►┐
│ 1
MUX ──► D ─►[FF_i]──► Q_i
│ 0
Q(i+1) ─►┘
▲
RIGHT / LEFT' (direction select)
| Direction control | Action |
|---|---|
| RIGHT = 1 | Shift right (Q_i ← Q_(i-1)) |
| RIGHT = 0 | Shift left (Q_i ← Q_(i+1)) |
8.3 Serial inputs at the ends
- Serial input for right shift (SIR) enters at the first flip-flop (Q0).
- Serial input for left shift (SIL) enters at the last flip-flop (Q_(n-1)).
8.4 Worked example (4-bit, initial Q0Q1Q2Q3 = 1011, serial inputs = 0)
| Operation | Q0 | Q1 | Q2 | Q3 |
|---|---|---|---|---|
| Initial | 1 | 0 | 1 | 1 |
| Shift right once | 0 | 1 | 0 | 1 |
| Shift left once (from initial) | 0 | 1 | 1 | 0 |
8.5 Useful side effect
Shifting the bits of a binary number left by one place doubles it, and shifting right by one place halves it (dropping the remainder), when the vacated bit is filled with 0.
9. Universal Shift Registers
9.1 Idea
A universal shift register combines everything: hold, shift right, shift left, and parallel load, all in one device, selected by mode-control inputs. It can therefore work as any of SISO, SIPO, PISO and PIPO.
9.2 How it's built
A 4:1 multiplexer at the D input of each flip-flop, driven by two select lines S1 S0:
Mux inputs for flip-flop i:
0 : Q_i (hold)
1 : Q_(i-1) (shift right)
2 : Q_(i+1) (shift left)
3 : P_i (parallel load)
9.3 Mode table
| S1 | S0 | Operation |
|---|---|---|
| 0 | 0 | Hold (no change) |
| 0 | 1 | Shift right |
| 1 | 0 | Shift left |
| 1 | 1 | Parallel load |
(This is the typical arrangement used by standard 4-bit universal shift register ICs such as the 74194, which also adds an asynchronous clear.)
9.4 Block diagram
┌───────────────────────────────┐
SIR ────►│ │
SIL ────►│ 4-BIT UNIVERSAL │
P3..P0 ─►│ SHIFT REGISTER ├──► Q3..Q0 (parallel out)
S1,S0 ──►│ │
CLK ────►│> │
CLEAR ──►│ │
└───────────────────────────────┘
9.5 Which operation gives which "classic" type?
| Wanted behaviour | How to use the universal register |
|---|---|
| SISO / SIPO | Mode 01 (or 10), feed the serial input, read last bit or all bits |
| PISO | Mode 11 once to load, then mode 01 to shift out |
| PIPO | Mode 11, read Q outputs directly |
| Temporary storage | Mode 00 |
10. Shift-Register Timing Diagrams
10.1 How to read them
- Signals are drawn against time, with the clock at the top.
- Every rising edge (for a positive-edge register) makes each bit move one place.
- The outputs change just after the edge, by the flip-flop's clock-to-Q delay.
- Each flip-flop output is a copy of the previous one delayed by one clock.
10.2 Timing diagram: 4-bit SISO, input stream 1 0 1 1 0 0 0
The shift register starts at 0000. Edges are numbered 1 to 7. Din is stable around each edge. Q values shown are those just after each edge.
Edge: 1 2 3 4 5 6 7
↓ ↓ ↓ ↓ ↓ ↓ ↓
CLK ‾‾__‾‾__‾‾__‾‾__‾‾__‾‾__‾‾__
Din ‾‾‾‾____‾‾‾‾‾‾‾‾____________
Q0 ‾‾‾‾____‾‾‾‾‾‾‾‾____________
Q1 ____‾‾‾‾____‾‾‾‾‾‾‾‾________
Q2 ________‾‾‾‾____‾‾‾‾‾‾‾‾____
Q3 (out) ____________‾‾‾‾____‾‾‾‾‾‾‾‾
10.3 State after each edge
| Edge | Din sampled | Q0 | Q1 | Q2 | Q3 |
|---|---|---|---|---|---|
| 1 | 1 | 1 | 0 | 0 | 0 |
| 2 | 0 | 0 | 1 | 0 | 0 |
| 3 | 1 | 1 | 0 | 1 | 0 |
| 4 | 1 | 1 | 1 | 0 | 1 |
| 5 | 0 | 0 | 1 | 1 | 0 |
| 6 | 0 | 0 | 0 | 1 | 1 |
| 7 | 0 | 0 | 0 | 0 | 1 |
10.4 What the diagram teaches
| Observation | Meaning |
|---|---|
| Q0 looks like Din delayed by one clock | Q0 captures Din at each edge |
| Q1 is Q0 delayed by one clock (and so on) | Each stage is a one-cycle delay |
| Q3 shows the input stream after 4 clocks | An n-bit SISO is an n-cycle delay line |
Reading Q0..Q3 after edge 4 gives 1 1 0 1 | That's the SIPO parallel output |
10.5 PISO timing in words
- Before the load edge, SHIFT/LOAD' = 0 and the parallel word is on P0..P3.
- At the load edge, the word is captured in all flip-flops at once.
- SHIFT/LOAD' is then set to 1; at each following edge the word marches toward the output and one bit appears at the serial output per clock.
10.6 Timing rules that still apply
- Each flip-flop's D input must obey setup and hold time around the edge. Because Q feeds the next D directly, the clock-to-Q delay of one stage must be at least the hold time of the next; a large clock skew between stages can break this and cause bits to "race through" two stages at once.
- Control signals (SHIFT/LOAD', mode bits S1 S0, direction) must be stable before the edge, like any other data input.
11. Ring and Johnson Registers
Both are shift registers with feedback: the output of the last flip-flop is connected back to the input of the first. Instead of data entering from outside, the pattern circulates. They are also called ring counter and Johnson (twisted-ring / switch-tail) counter.
11.1 Ring register (ring counter)
Feedback: Q_(n-1) → D0 (direct connection).
┌──────────────────────────────────────────┐
│ │
└─►[FF0]─►[FF1]─►[FF2]─►[FF3]──────────────┘
▲ ▲ ▲ ▲
└──────┴──────┴──────┘ CLK
Usually initialised to a single 1 (a "one-hot" pattern), e.g. 1000. That 1 just circulates.
4-bit sequence (Q0 Q1 Q2 Q3):
| Clock | Q0 | Q1 | Q2 | Q3 |
|---|---|---|---|---|
| 0 | 1 | 0 | 0 | 0 |
| 1 | 0 | 1 | 0 | 0 |
| 2 | 0 | 0 | 1 | 0 |
| 3 | 0 | 0 | 0 | 1 |
| 4 | 1 | 0 | 0 | 0 |
Properties
- n flip-flops → n states (mod-n).
- Only one flip-flop is HIGH at a time (one-hot), so each state is available directly at a flip-flop output, with no decoding logic.
- Output frequency at any Q = f_clk / n.
- It must be initialised properly (e.g. via preset/clear, or by starting with a load). Otherwise it may start in an invalid pattern (all 0s or several 1s), which just circulates forever.
- Inefficient use of flip-flops: only n of the 2ⁿ possible patterns are used.
11.2 Johnson register (twisted-ring counter)
Feedback: Q'_(n-1) → D0 (the complement of the last output goes back, hence "twisted").
┌────────────────[NOT]─────────────────────┐
│ │
└─►[FF0]─►[FF1]─►[FF2]─►[FF3]──────────────┘
Starts from all 0s. The register fills with 1s from the left, then fills with 0s again.
4-bit sequence (Q0 Q1 Q2 Q3):
| Clock | Q0 | Q1 | Q2 | Q3 |
|---|---|---|---|---|
| 0 | 0 | 0 | 0 | 0 |
| 1 | 1 | 0 | 0 | 0 |
| 2 | 1 | 1 | 0 | 0 |
| 3 | 1 | 1 | 1 | 0 |
| 4 | 1 | 1 | 1 | 1 |
| 5 | 0 | 1 | 1 | 1 |
| 6 | 0 | 0 | 1 | 1 |
| 7 | 0 | 0 | 0 | 1 |
| 8 | 0 | 0 | 0 | 0 |
Properties
- n flip-flops → 2n states (mod-2n): twice the count of a ring counter with the same hardware.
- Output frequency at any Q = f_clk / 2n.
- Decoding each state needs only a 2-input AND gate (look at just two adjacent bits).
- Only 2n of the 2ⁿ patterns are valid; a 4-bit Johnson uses 8 of 16. The other 8 are unused states, which form separate loops, so the counter should be initialised (cleared) or have extra logic to be self-correcting.
11.3 Ring vs Johnson
| Feature | Ring counter | Johnson counter |
|---|---|---|
| Feedback | Q_(n-1) → D0 | Q'_(n-1) → D0 |
| Initial state | One-hot (e.g. 1000) | All zeros |
| Number of states (n FFs) | n | 2n |
| Output frequency | f / n | f / 2n |
| Decoding | None (one-hot) | 2-input AND per state |
| Unused states (n = 4) | 12 | 8 |
| Flip-flop efficiency | Lower | Higher |
| Pattern type | Single 1 circulating | Block of 1s then block of 0s |
11.4 Typical uses
- Ring: generating timing / sequencing pulses one after another (e.g., enabling one stage at a time in a control sequence), one-hot state storage.
- Johnson: frequency division by 2n, sequence generators, decoded timing signals using fewer gates.
12. Applications in Data Storage and Transfer
12.1 Data storage
| Use | How registers help |
|---|---|
| CPU registers | Parallel registers hold operands, results, addresses and instructions while the processor works |
| Temporary buffers | A PIPO register holds a word between two circuits that run at different moments |
| Holding output | A register keeps a value steady on its outputs for as long as needed (using the load-control hold) |
12.2 Data transfer
| Use | How shift registers help |
|---|---|
| Serial-to-parallel conversion | A SIPO collects incoming serial bits into a word the rest of the system reads in parallel (e.g. receiving serial data) |
| Parallel-to-serial conversion | A PISO loads a parallel word, then sends it out one bit per clock (e.g. transmitting serial data) |
| Reducing wires | Sending a wide word over one line saves pins and cable |
| I/O expansion | Shift registers can add extra output pins (SIPO) or input pins (PISO) to a system with few I/O lines |
| Register-to-register moves | A parallel register copies its contents into another in one clock |
12.3 Data manipulation and timing
| Use | Description |
|---|---|
| Delay lines | A SISO delays a digital signal by n clock periods |
| Arithmetic | Shifting left/right multiplies/divides by 2 (bidirectional and universal registers) |
| Sequence / timing generation | Ring and Johnson counters produce repeating, evenly-spaced control pulses |
| Frequency division | Johnson counters divide the clock by 2n |
12.4 Which register for which job?
| Task | Best choice |
|---|---|
| Keep a word for later use | Parallel (PIPO) register with load control |
| Receive a serial stream as a word | SIPO |
| Send a word over a single wire | PISO |
| Delay a bit stream | SISO |
| Need left/right shifting | Bidirectional |
| Need all of the above in one chip | Universal |
| Generate timing pulses in sequence | Ring (or Johnson) |
13. Quick Revision Cheat Sheet
Core ideas
| Topic | Remember this |
|---|---|
| Register | n flip-flops + common clock = n-bit storage |
| Parallel register | Loads all bits in 1 clock; load control = mux with Q feedback |
| Shift register | Each Q feeds the next D; bits move one place per clock |
| SISO | Serial in, serial out; n-clock delay line |
| SIPO | Serial in, parallel out; serial → parallel conversion |
| PISO | Parallel in, serial out; needs SHIFT/LOAD' mux; parallel → serial |
| PIPO | Parallel in, parallel out; plain storage; fastest |
| Bidirectional | 2:1 mux per bit chooses left/right neighbour |
| Universal | 4:1 mux per bit: hold / right / left / load (S1 S0 = 00/01/10/11) |
| Ring counter | Q_last → D_first; one-hot; n states; no decoding |
| Johnson counter | Q'_last → D_first; 2n states; 2-input AND decoding |
Key formulas
Register capacity : n flip-flops → n bits (2ⁿ values)
SISO delay : n clock cycles
Ring counter (n FFs) : n states, f_out = f_clk / n
Johnson counter (n FFs) : 2n states, f_out = f_clk / 2n
Parallel load, per bit : D_i = LOAD·I_i + LOAD'·Q_i
PISO, per bit : D_i = SHIFT'·P_i + SHIFT·Q_(i-1)
Common mistakes to avoid
- Thinking bits "rush through" a whole shift register in one clock. They move exactly one place because all flip-flops sample at the same edge.
- Forgetting that the first bit in reaches the output of an n-bit register only after n clocks.
- Mixing up ring (direct feedback, n states) and Johnson (inverted feedback, 2n states).
- Not initialising a ring or Johnson counter, so it starts in an invalid state and never recovers.
- Reading a SIPO output at the wrong time. The outputs keep changing on every clock.
- Assuming PIPO needs shifting. It is just a parallel register.
Likely quick-fire questions
- How many flip-flops are needed to store an 8-bit word? Eight.
- Why is a Johnson counter more efficient than a ring counter? It gives 2n states from n flip-flops (vs n).
- How does a PISO register switch between loading and shifting? A SHIFT/LOAD' control selects either the parallel input or the previous flip-flop's output at each D input.
- What makes a shift register "universal"? Mode-select lines allow hold, shift right, shift left and parallel load in one device.
- What is the main use of SIPO and PISO? Serial-to-parallel and parallel-to-serial data conversion.
#Counters#
Study notes on counters: sequential circuits that step through a fixed list of states, one step per clock pulse. We cover how they are built (ripple and synchronous), the different counting styles (up, down, modulus, decade, ring, Johnson, programmable), how to cascade and design them, how to read their timing diagrams, why glitches appear, and how counters divide frequency.
Table of Contents
- Counter Fundamentals
- Asynchronous (Ripple) Counters
- Synchronous Counters
- Up, Down and Up/Down Counters
- Modulus and Divide-by-N Counters
- Decade and BCD Counters
- Ring Counters
- Johnson Counters
- Programmable Counters
- Cascaded Counters
- Counter Design Using Flip-Flops
- Counter Timing Diagrams
- Propagation Delay and Glitches in Counters
- Frequency Division
- Quick Revision Cheat Sheet
1. Counter Fundamentals
1.1 What is a counter?
A counter is a sequential circuit made of flip-flops that goes through a predetermined sequence of states each time it receives a clock (or input) pulse. The state of the flip-flops is the count.
Analogy: a car's odometer. Every pulse moves it one step forward, and after the last value it wraps around to the start.
1.2 Key terms
| Term | Meaning |
|---|---|
| State / count | The binary value held in the flip-flops |
| Modulus (MOD) | Number of distinct states in one full cycle. A MOD-N counter counts N states, then repeats |
| Free-running | Counts continuously in its natural binary sequence |
| Up / Down counter | Count increases / decreases with each pulse |
| Terminal count | The last state in the sequence (e.g. 1111 for a 4-bit up counter) |
| Asynchronous (ripple) | Flip-flops do not share one clock; each is clocked by the previous stage |
| Synchronous | All flip-flops share the same clock |
1.3 How many flip-flops?
- n flip-flops can represent up to 2ⁿ states, so a natural binary counter has
MOD = 2ⁿ. - To build a MOD-N counter you need the smallest n with
2ⁿ ≥ N, i.e.n = ⌈log₂ N⌉.
| Flip-flops (n) | Maximum states (2ⁿ) | Count range |
|---|---|---|
| 2 | 4 | 0 to 3 |
| 3 | 8 | 0 to 7 |
| 4 | 16 | 0 to 15 |
| 8 | 256 | 0 to 255 |
1.4 The flip-flop doing the work
Counters usually use T flip-flops (toggle) or JK flip-flops with J = K = 1 (also toggle). Remember:
T = 0 → hold T = 1 → toggle Q⁺ = T ⊕ Q
Each bit of a binary counter toggles at half the rate of the bit before it. That is the pattern both ripple and synchronous counters exploit.
2. Asynchronous (Ripple) Counters
2.1 Idea
Only the first flip-flop gets the external clock. Each following flip-flop is clocked by the output of the previous one. The change "ripples" through the chain, hence the name.
2.2 3-bit ripple up counter (negative-edge-triggered flip-flops)
1 (J=K=1) 1 1
│ │ │
CLK ─○>[ FF0 ]─ Q0 ─○>[ FF1 ]─ Q1 ─○>[ FF2 ]─ Q2
- Every flip-flop is set to toggle (T = 1, or J = K = 1).
- FF0 toggles on every falling edge of CLK.
- FF1 toggles on every falling edge of Q0.
- FF2 toggles on every falling edge of Q1.
Count sequence (Q2 Q1 Q0):
| Clock pulse | Q2 | Q1 | Q0 | Decimal |
|---|---|---|---|---|
| 0 | 0 | 0 | 0 | 0 |
| 1 | 0 | 0 | 1 | 1 |
| 2 | 0 | 1 | 0 | 2 |
| 3 | 0 | 1 | 1 | 3 |
| 4 | 1 | 0 | 0 | 4 |
| 5 | 1 | 0 | 1 | 5 |
| 6 | 1 | 1 | 0 | 6 |
| 7 | 1 | 1 | 1 | 7 |
| 8 | 0 | 0 | 0 | 0 (wraps) |
2.3 Why it counts correctly
A bit's falling edge (1 → 0) is exactly the moment the next higher bit must toggle (a carry). A negative-edge flip-flop watching the previous Q therefore toggles only on a carry.
2.4 Choosing the clock connection
| Counter type | Negative-edge FFs: next clock = | Positive-edge FFs: next clock = |
|---|---|---|
| Up | Q of previous stage | Q' of previous stage |
| Down | Q' of previous stage | Q of previous stage |
2.5 Advantages and disadvantages
| Advantages | Disadvantages |
|---|---|
| Very simple, minimal hardware (no extra gates) | Delays add up stage by stage (see Section 13) |
| Easy to extend by adding a flip-flop | Slow: limited maximum frequency |
| Lower power on higher stages (they toggle less) | Glitches (temporary wrong counts) while it ripples |
3. Synchronous Counters
3.1 Idea
All flip-flops receive the same clock and change at the same instant. A flip-flop is told whether to toggle by gating logic that looks at the lower bits.
3.2 The rule for an up counter
A bit toggles only when all lower bits are 1 (that is exactly when a carry reaches it).
For T flip-flops (3-bit and 4-bit up counter):
T0 = 1
T1 = Q0
T2 = Q0 · Q1
T3 = Q0 · Q1 · Q2
3.3 3-bit synchronous up counter circuit
1 ──────────────────────►T0┐
┌──────[FF0]── Q0 ─┬──────────────────┐
│ │ │
Q0 ──────────────────────────────►T1┐ │ │
[FF1]── Q1 ─┐ │
▼ ▼
[ AND ] ◄── Q0 ────┘
│
└────►T2┐
[FF2]── Q2
CLK ───────► (connected to ALL flip-flops)
Reading it simply: FF0 always toggles, FF1 toggles when Q0 = 1, FF2 toggles when Q0·Q1 = 1. One clock drives all.
3.4 Synchronous vs asynchronous at a glance
| Feature | Asynchronous (ripple) | Synchronous |
|---|---|---|
| Clock | Only the first FF gets CLK | All FFs get the same CLK |
| Delay | n × t_pd (accumulates) | One FF delay + gate delay |
| Max frequency | Low | Higher |
| Hardware | Fewer gates | Extra gates needed |
| Glitches | Many transient states | Far fewer (bits change together) |
| Design effort | Very easy | Needs logic design |
| Typical use | Simple, low-speed counting | High-speed, reliable counting |
4. Up, Down and Up/Down Counters
4.1 Up counter
Counts 0, 1, 2, ... , max, 0, .... (Covered in Sections 2 and 3.)
4.2 Down counter
Counts max, max−1, ... , 1, 0, max, ....
3-bit down counter sequence (Q2 Q1 Q0):
111 → 110 → 101 → 100 → 011 → 010 → 001 → 000 → 111 ...
Why it works: a bit must toggle when all lower bits are 0 (a borrow).
- Synchronous (T flip-flops):
T0 = 1
T1 = Q0'
T2 = Q0' · Q1'
T3 = Q0' · Q1' · Q2'
- Asynchronous: clock the next stage from Q' (negative-edge FFs), as in the table in Section 2.4.
4.3 Up/Down counter
One counter that can count either way, chosen by a control input M (say M = 1 → up, M = 0 → down).
Synchronous version (T flip-flops):
T0 = 1
T1 = M·Q0 + M'·Q0'
T2 = M·Q0·Q1 + M'·Q0'·Q1'
T3 = M·Q0·Q1·Q2 + M'·Q0'·Q1'·Q2'
Asynchronous version (negative-edge FFs): a 2:1 multiplexer chooses the clock of the next stage:
CLK(i+1) = M · Q_i + M' · Q_i'
| M | Next stage is clocked by | Result |
|---|---|---|
| 1 | Q of previous | Counts up |
| 0 | Q' of previous | Counts down |
5. Modulus and Divide-by-N Counters
5.1 Modulus
A MOD-N counter has N states and counts 0 to N − 1, then returns to 0.
- A natural n-bit counter is MOD-2ⁿ.
- To get a MOD-N where N is not a power of 2, we skip the extra states ("truncate" the sequence).
5.2 Divide-by-N
A MOD-N counter produces an output at the clock frequency divided by N:
f_out = f_clk / N
Hence "MOD-N counter" and "divide-by-N counter" mean the same thing.
5.3 Asynchronous MOD-N using the clear input (the "reset" method)
- Choose the smallest n with
2ⁿ ≥ N. - Build a normal ripple counter with that many flip-flops (with asynchronous clear).
- Decode the state N (the first unwanted state) using a gate.
- Feed the decoder output to the clear inputs so the counter instantly returns to 0.
Example: MOD-6 counter (counts 0 to 5)
- 3 flip-flops are needed (
2² = 4 < 6 ≤ 8). - First unwanted state = 6 =
110. Detect it with a NAND of Q2 and Q1 (Q0 need not be checked because 110 is the first state in the sequence where Q2 = Q1 = 1). - The NAND output drives active-low CLEAR.
Q2 ──┐
├─[NAND]──► CLEAR' (to all flip-flops)
Q1 ──┘
| Count | Q2 | Q1 | Q0 | Note |
|---|---|---|---|---|
| 0 | 0 | 0 | 0 | |
| 1 | 0 | 0 | 1 | |
| 2 | 0 | 1 | 0 | |
| 3 | 0 | 1 | 1 | |
| 4 | 1 | 0 | 0 | |
| 5 | 1 | 0 | 1 | |
| (6) | 1 | 1 | 0 | Appears briefly, triggers clear, back to 000 |
Drawback: the unwanted state is visible for a very short time (a glitch, see Section 13). Also, flip-flops clear at slightly different speeds, so the clear signal may disappear before the slowest flip-flop clears.
5.4 Synchronous MOD-N
Modify the next-state logic so that after state N − 1 the next state is 0 (no unwanted state is ever entered). Section 11 shows the complete design method with a MOD-6 example.
5.5 Unused states
A MOD-N counter built from n flip-flops has 2ⁿ − N unused states. A good design ensures that if the counter ever lands in one, it returns to a valid state on its own (self-starting / self-correcting).
6. Decade and BCD Counters
6.1 Decade counter
A decade counter is a MOD-10 counter: it has 10 states and produces one output pulse every 10 input pulses (divide-by-10).
6.2 BCD counter
A BCD counter is a decade counter whose 10 states are the binary-coded-decimal digits 0 to 9:
0000 → 0001 → 0010 → ... → 1000 → 1001 → 0000 ...
It uses 4 flip-flops and skips 1010 to 1111.
6.3 Asynchronous BCD (decade) ripple counter
Start with a 4-bit ripple counter. After 1001 (9) the counter would go to 1010 (10). Detect that state and clear.
- First state where Q3 = 1 and Q1 = 1 is
1010(since 1000 and 1001 have Q1 = 0). - So
CLEAR' = (Q3 · Q1)': a NAND of Q3 and Q1 to the active-low clear.
Q3 ──┐
├─[NAND]──► CLEAR'
Q1 ──┘
6.4 Synchronous BCD counter (T flip-flops)
T0 = 1
T1 = Q3' · Q0
T2 = Q1 · Q0
T3 = Q2 · Q1 · Q0 + Q3 · Q0
Check on the critical transitions:
0111 → 1000: T3 = Q2Q1Q0 = 1 ✓ (bit 3 sets), T2 = Q1Q0 = 1 ✓, T1 = Q3'Q0 = 1 ✓, T0 = 1 ✓ (all lower bits clear).1001 → 0000: T3 = Q3Q0 = 1 ✓ (bit 3 clears), T1 = Q3'Q0 = 0 ✓ (stays 0), T2 = Q1Q0 = 0 ✓, T0 = 1 ✓.
6.5 BCD sequence table
| Count | Q3 | Q2 | Q1 | Q0 |
|---|---|---|---|---|
| 0 | 0 | 0 | 0 | 0 |
| 1 | 0 | 0 | 0 | 1 |
| 2 | 0 | 0 | 1 | 0 |
| 3 | 0 | 0 | 1 | 1 |
| 4 | 0 | 1 | 0 | 0 |
| 5 | 0 | 1 | 0 | 1 |
| 6 | 0 | 1 | 1 | 0 |
| 7 | 0 | 1 | 1 | 1 |
| 8 | 1 | 0 | 0 | 0 |
| 9 | 1 | 0 | 0 | 1 |
| 0 | 0 | 0 | 0 | 0 |
6.6 Uses
- Counting in decimal (one BCD counter per digit, see cascading in Section 10).
- Divide-by-10 stages in frequency division.
7. Ring Counters
7.1 Structure
A ring counter is a shift register whose last output feeds the first input (Q_last → D_first). A single 1 circulates around the ring.
┌──────────────────────────────────────────┐
│ │
└─►[FF0]─►[FF1]─►[FF2]─►[FF3]──────────────┘
▲ ▲ ▲ ▲
└──────┴──────┴──────┘ CLK
7.2 Sequence (4-bit, Q0 Q1 Q2 Q3, initial 1000)
| Clock | Q0 | Q1 | Q2 | Q3 |
|---|---|---|---|---|
| 0 | 1 | 0 | 0 | 0 |
| 1 | 0 | 1 | 0 | 0 |
| 2 | 0 | 0 | 1 | 0 |
| 3 | 0 | 0 | 0 | 1 |
| 4 | 1 | 0 | 0 | 0 |
7.3 Properties
- n flip-flops → MOD-n (only n states).
- One-hot output, so each state is available directly with no decoder.
- Output frequency at any Q = f_clk / n, with a duty cycle of 1/n.
- It needs initialisation (a single 1 loaded using preset/clear). Otherwise it may start in an invalid pattern (such as all 0s) and stay there.
- Uses only n of the 2ⁿ possible states: inefficient.
7.4 Self-correcting ring counter
To make a 4-bit ring counter start itself from any state, feed the first flip-flop with:
D0 = (Q0 + Q1 + Q2)'
A 1 is inserted whenever the first three bits are all 0, and extra 1s shift out, so the counter always ends up in the single-1 pattern.
8. Johnson Counters
8.1 Structure
A Johnson counter (twisted-ring, switch-tail counter) feeds the inverted last output to the first input (Q'_last → D_first).
┌────────────────[NOT]─────────────────────┐
│ │
└─►[FF0]─►[FF1]─►[FF2]─►[FF3]──────────────┘
8.2 Sequence (4-bit, Q0 Q1 Q2 Q3, initial 0000)
| Clock | Q0 | Q1 | Q2 | Q3 |
|---|---|---|---|---|
| 0 | 0 | 0 | 0 | 0 |
| 1 | 1 | 0 | 0 | 0 |
| 2 | 1 | 1 | 0 | 0 |
| 3 | 1 | 1 | 1 | 0 |
| 4 | 1 | 1 | 1 | 1 |
| 5 | 0 | 1 | 1 | 1 |
| 6 | 0 | 0 | 1 | 1 |
| 7 | 0 | 0 | 0 | 1 |
| 8 | 0 | 0 | 0 | 0 |
8.3 Properties
- n flip-flops → MOD-2n (twice the states of a ring counter).
- Output frequency at any Q = f_clk / 2n, with a 50% duty cycle.
- Only one bit changes per clock, which makes decoding clean and nearly glitch-free.
- Only 2n of the 2ⁿ states are valid (a 4-bit Johnson counter uses 8 of 16). The other states form unwanted loops, so the counter must be cleared at start or have correction logic.
8.4 Decoding: just a 2-input gate per state
| State (Q0 Q1 Q2 Q3) | Decoding term |
|---|---|
| 0000 | Q0'·Q3' |
| 1000 | Q0·Q1' |
| 1100 | Q1·Q2' |
| 1110 | Q2·Q3' |
| 1111 | Q0·Q3 |
| 0111 | Q0'·Q1 |
| 0011 | Q1'·Q2 |
| 0001 | Q2'·Q3 |
8.5 Ring vs Johnson
| Feature | Ring | Johnson |
|---|---|---|
| Feedback | Q_last | Q'_last |
| Start pattern | One-hot (1000) | All zeros (0000) |
| States (n FFs) | n | 2n |
| Output frequency | f / n | f / 2n |
| Output duty cycle | 1/n | 50% |
| Decoding | None needed | 2-input gate per state |
| Bits changing per clock | 2 (one 1 leaves, one arrives) | 1 |
| Unused states (n = 4) | 12 | 8 |
9. Programmable Counters
9.1 Idea
A programmable counter lets you choose the modulus (or the starting value) by supplying a number on parallel data inputs. It is built from a counter with a parallel load feature.
9.2 Required inputs
| Input | Role |
|---|---|
| Preset data (P) | The number to load |
| LOAD | When active, the counter takes P instead of counting |
| Terminal-count output (TC) | Goes active at the last state of the count range |
9.3 How the modulus is set (up counter, load on terminal count)
- Counter counts up from the loaded value P to its maximum (
2ⁿ − 1). - At the terminal count, TC activates LOAD.
- On the next clock the counter reloads P and repeats.
Modulus = 2ⁿ − P
Example: 4-bit counter, P = 0110 (6). Sequence:
6 → 7 → 8 → 9 → 10 → 11 → 12 → 13 → 14 → 15 → (reload) 6 ...
That is 10 states → a MOD-10 (divide-by-10) counter, because 16 − 6 = 10.
9.4 Down-counting version
A down counter can be loaded with a number and made to reload when it reaches zero. The modulus is set directly by the loaded value, adjusted by one depending on whether the reload happens at the zero state or one state before it (loading N − 1 and reloading at 0 gives N states).
9.5 Synchronous vs asynchronous load
| Load type | Behaviour |
|---|---|
| Synchronous load | Data enters at the next clock edge. No unwanted states and no glitches. Preferred |
| Asynchronous load | Data enters immediately when LOAD is active, independent of the clock. May create a brief glitch at the terminal state |
9.6 Why they're useful
The same hardware can divide by different numbers just by changing P. This is the basis of programmable frequency dividers and programmable timers.
10. Cascaded Counters
10.1 What is cascading?
Cascading connects counters in series so the overall modulus is the product of the individual moduli:
MOD_total = MOD₁ × MOD₂ × MOD₃ × ...
10.2 Examples
| Cascade | Total modulus |
|---|---|
| Two 4-bit binary counters (MOD-16 × MOD-16) | 256 (an 8-bit counter) |
| Two decade counters (MOD-10 × MOD-10) | 100 |
| Decade × MOD-6 | 60 (e.g. a seconds counter, 0 to 59) |
| Three decade counters | 1000 |
10.3 Two ways to cascade
(a) Ripple (asynchronous) cascade: the terminal-count / carry output of the first counter is used as the clock of the next.
CLK ─►[ Counter 1 ]─ TC1 ─►[ Counter 2 ]─ TC2 ─► ...
- Simple.
- Delays accumulate through the stages (slow, possibly glitchy).
(b) Synchronous cascade: all counters share the same clock, and the terminal count of the lower counter enables the next counter:
CLK ─────┬──────────────┬─────────────
▼ ▼
[ Counter 1 ]──TC1─►EN [ Counter 2 ]──TC2─►EN [ Counter 3 ]
EN1 = 1
- The higher counter advances only on the clock edge when the lower counter is at its terminal count.
- For three or more stages:
EN₃ = TC₁ · TC₂(the higher stage counts only when all lower stages are at terminal count). - Faster and cleaner than ripple cascading.
10.4 Frequency view
The final stage's output frequency is the input clock divided by the total modulus:
f_out = f_clk / (MOD₁ × MOD₂ × ...)
10.5 Example: seconds counter (MOD-60)
A 1 Hz clock feeds a MOD-10 counter (units of seconds) cascaded with a MOD-6 counter (tens of seconds). The MOD-10 stage's terminal count (at 9) lets the MOD-6 stage advance by 1. The pair counts 00 to 59, then wraps to 00, and its carry output is a 1-pulse-per-minute signal.
11. Counter Design Using Flip-Flops
11.1 General procedure (synchronous design)
- Decide the sequence of states and the number of flip-flops (
n = ⌈log₂ N⌉). - Draw the state diagram / state table (present state → next state).
- Choose the flip-flop type (T, JK, D, SR).
- Using the flip-flop's excitation table, find the inputs needed for each transition.
- Treat unused states as don't-cares (X).
- Simplify the input equations using K-maps.
- Draw the circuit: shared clock, input logic, flip-flops.
- Check self-starting: from each unused state, make sure the counter reaches a valid state.
11.2 Excitation tables you need
| Q → Q⁺ | T | D | JK (J K) | SR (S R) |
|---|---|---|---|---|
| 0 → 0 | 0 | 0 | 0 X | 0 X |
| 0 → 1 | 1 | 1 | 1 X | 1 0 |
| 1 → 0 | 1 | 0 | X 1 | 0 1 |
| 1 → 1 | 0 | 1 | X 0 | X 0 |
11.3 Worked example: synchronous MOD-6 up counter using T flip-flops
Sequence: 0 → 1 → 2 → 3 → 4 → 5 → 0. Three flip-flops (Q2 Q1 Q0). States 110 and 111 are unused (don't care).
Excitation table (T = Q ⊕ Q⁺ for each bit)
| Present (Q2 Q1 Q0) | Next (Q2⁺ Q1⁺ Q0⁺) | T2 | T1 | T0 |
|---|---|---|---|---|
| 000 | 001 | 0 | 0 | 1 |
| 001 | 010 | 0 | 1 | 1 |
| 010 | 011 | 0 | 0 | 1 |
| 011 | 100 | 1 | 1 | 1 |
| 100 | 101 | 0 | 0 | 1 |
| 101 | 000 | 1 | 0 | 1 |
| 110 | XXX | X | X | X |
| 111 | XXX | X | X | X |
Simplification (K-maps)
- T0 = 1 in every valid state →
T0 = 1 - T1 = 1 only for 001 and 011 →
T1 = Q2' · Q0 - T2 = 1 for 011 and 101 (don't cares at 110, 111) →
T2 = Q0 · (Q1 + Q2)
Circuit summary
T0 = 1
T1 = Q2' · Q0
T2 = Q0 · (Q1 + Q2)
All flip-flops: same CLK
Self-starting check (unused states):
110: T0 = 1, T1 = 0, T2 = 0 → next111111: T0 = 1, T1 = 0, T2 = 1 → next010✓ (valid state)
So the counter recovers from both unused states within two clocks.
11.4 Design with other flip-flop types
The procedure is the same. Only the excitation table changes:
- D flip-flop:
D = Q⁺(the equation is just the next-state function). - JK flip-flop: use the J and K columns; the many don't cares often give simpler logic.
12. Counter Timing Diagrams
12.1 How to read them
- The clock is at the top.
- Each flip-flop output is a waveform; in a binary counter, Q0 toggles every clock, Q1 every 2 clocks, Q2 every 4 clocks, and so on.
- Each output has half the frequency of the previous one.
12.2 3-bit ripple up counter (negative-edge triggered), 8 clock cycles
Cycle: 1 2 3 4 5 6 7 8
CLK ‾‾__‾‾__‾‾__‾‾__‾‾__‾‾__‾‾__‾‾__
Q0 __‾‾‾‾____‾‾‾‾____‾‾‾‾____‾‾‾‾__
Q1 ______‾‾‾‾‾‾‾‾________‾‾‾‾‾‾‾‾__
Q2 ______________‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾__
- Q0 changes at every falling edge of CLK.
- Q1 changes at every falling edge of Q0.
- Q2 changes at every falling edge of Q1.
- (In a real ripple counter each output changes slightly later than the one before it by one propagation delay. The diagram above is the ideal view.)
12.3 State after each falling edge of CLK
| Falling edge | Q2 | Q1 | Q0 | Count |
|---|---|---|---|---|
| 1 | 0 | 0 | 1 | 1 |
| 2 | 0 | 1 | 0 | 2 |
| 3 | 0 | 1 | 1 | 3 |
| 4 | 1 | 0 | 0 | 4 |
| 5 | 1 | 0 | 1 | 5 |
| 6 | 1 | 1 | 0 | 6 |
| 7 | 1 | 1 | 1 | 7 |
| 8 | 0 | 0 | 0 | 0 |
12.4 Frequency relationship seen in the diagram
| Signal | Frequency | Period |
|---|---|---|
| CLK | f | T |
| Q0 | f / 2 | 2T |
| Q1 | f / 4 | 4T |
| Q2 | f / 8 | 8T |
12.5 Timing for other counters (in words)
- Synchronous counter: all outputs change together right after the same clock edge (by one clock-to-Q delay), with no staggered ripple.
- MOD-N counter: the diagram shows the count running from 0 to N − 1 and returning to 0. For a clear-based design a very short spike of state N is visible on the affected outputs.
- Ring counter: a single HIGH pulse, one clock wide, steps from Q0 to Q1 to Q2 and so on.
- Johnson counter: each output is a 50% duty-cycle square wave, each shifted by one clock from its neighbour.
13. Propagation Delay and Glitches in Counters
13.1 Propagation delay in ripple counters
Each flip-flop has a propagation (clock-to-Q) delay t_pd. In a ripple counter the delays add up, because each stage waits for the previous one:
Total ripple delay = n × t_pd
Consequences
- The counter output is not valid until the last stage finishes.
- The clock period must be longer than the total ripple delay (plus decoding time if the count is decoded):
T_clk > n × t_pd → f_max ≈ 1 / (n × t_pd)
Example: 4 flip-flops, t_pd = 20 ns → total delay 80 ns → f_max ≈ 12.5 MHz.
13.2 Propagation delay in synchronous counters
All flip-flops change together, so the delay does not accumulate with the number of stages. The limit comes from one flip-flop plus the input gating logic:
T_clk ≥ t_cq + t_gate + t_su → f_max = 1 / (t_cq + t_gate + t_su)
Example: t_cq = 20 ns, AND gate 10 ns, t_su = 5 ns → 35 ns → f_max ≈ 28.6 MHz, faster than the ripple version above.
13.3 What is a glitch?
A glitch is a very short, unwanted pulse on a signal caused by outputs changing at slightly different times.
13.4 Glitches in ripple counters
Because bits change one after another, the counter passes through false intermediate states between valid counts. Example, 011 → 100 (3 → 4):
011 → 010 → 000 → 100
Q0 falls Q1 falls Q2 rises
first next last
For a short time the counter shows 010 and 000, which are not part of the true transition. Worst case 111 → 000 passes through 110 and 100.
If a decoder looks at these outputs, it may produce a false output pulse (a decoding glitch) when it sees a temporary state.
13.5 Glitches in MOD-N counters that use clear
- The unwanted state N appears briefly before the clear signal removes it. Any circuit reading that output sees a short spike.
- The flip-flops may not clear at exactly the same speed. If the fastest one clears and removes the decoded state before the slowest has cleared, the slower flip-flop may fail to clear.
13.6 Glitches in synchronous counters
Even synchronous counters can glitch when several bits change at once (like 0111 → 1000), because the flip-flops' delays are not identical. The wrong code lasts only a few nanoseconds, but a decoder can still react.
13.7 Ways to reduce the problems
| Problem | Remedy |
|---|---|
| Accumulated ripple delay | Use a synchronous counter |
| Decoder glitches | Strobe (enable) the decoder only after the outputs have settled |
| Glitchy decoded output | Register the decoded signal in a flip-flop so only clean values are used |
| Spike from the clear method | Use a synchronous load/reset (acts at the clock edge) instead of asynchronous clear |
| Multi-bit transitions | Use a counter in which only one bit changes per step, such as a Johnson counter |
14. Frequency Division
14.1 The idea
A counter is a natural frequency divider: each output toggles at a lower rate than the clock.
- Each toggle (T) flip-flop divides its input frequency by 2.
- n flip-flops in a chain divide by 2ⁿ.
- Any MOD-N counter divides by N.
14.2 Binary ripple counter as a divider
| Output | Frequency |
|---|---|
| Q0 | f / 2 |
| Q1 | f / 4 |
| Q2 | f / 8 |
| Q(n−1) | f / 2ⁿ |
14.3 Dividing by numbers that aren't powers of 2
Use a MOD-N counter (truncated count, decade counter, programmable counter): f_out = f_in / N.
14.4 Duty cycle
| Divider | Output duty cycle |
|---|---|
| Divide by 2ⁿ from a binary counter's last output | 50% |
| MOD-N with N not a power of 2 (e.g. decade, output at Q3) | Not 50% (decade: Q3 is HIGH for only 2 of 10 states = 20%) |
| Ring counter output | 1/n |
| Johnson counter output | 50% |
To get a 50% duty cycle from a divide-by-N output, a final divide-by-2 flip-flop can be added after it (the output then has frequency f / 2N and a symmetrical waveform).
14.5 Worked examples
Example 1: 1 MHz clock, find 1 kHz.
Ratio = 1000 → three cascaded decade counters (10 × 10 × 10 = 1000) → 1 MHz / 1000 = 1 kHz.
Example 2: 32 768 Hz source, find 1 Hz.
32 768 = 2¹⁵, so 15 flip-flops in a chain give exactly 1 Hz.
Example 3: 4-bit programmable counter loaded with 6 → MOD-10 → divides the input by 10.
15. Quick Revision Cheat Sheet
Core ideas
| Topic | Remember this |
|---|---|
| Counter | Flip-flops stepping through a fixed state sequence |
| MOD-N | N states, f_out = f_clk / N, needs ⌈log₂ N⌉ flip-flops |
| Ripple (async) | Each FF clocked by the previous; simple, slow, glitchy |
| Synchronous | Common clock + gating; faster, cleaner, more logic |
| Up counter (sync, T FFs) | T_i = Q0·Q1·...·Q(i−1) |
| Down counter (sync, T FFs) | T_i = Q0'·Q1'·...·Q(i−1)' |
| Up/down | Mode input M selects Q or Q' paths |
| Async MOD-N | Decode state N, clear all FFs |
| BCD / decade | MOD-10, counts 0000 to 1001, async clear on Q3·Q1 |
| Ring | Q_last → D_first, n states, one-hot |
| Johnson | Q'_last → D_first, 2n states, 50% duty cycle |
| Programmable | Parallel load; MOD = 2ⁿ − P (up count, reload at terminal count) |
| Cascaded | MOD_total = MOD₁ × MOD₂ × ... |
| Ripple delay | n × t_pd |
| Frequency division | n FFs → f / 2ⁿ |
Key formulas
States with n flip-flops : 2ⁿ
Flip-flops for MOD-N : n = ⌈log₂ N⌉
Divide-by-N frequency : f_out = f_clk / N
Unused states (MOD-N, n FFs) : 2ⁿ − N
Ripple counter max frequency : f_max ≈ 1 / (n × t_pd)
Sync counter max frequency : f_max = 1 / (t_cq + t_gate + t_su)
Ring counter : n states, f / n
Johnson counter : 2n states, f / 2n
Programmable (up, load P) : MOD = 2ⁿ − P
Cascaded counters : MOD = MOD₁ × MOD₂ × ...
T flip-flop excitation : T = Q ⊕ Q⁺
Common mistakes to avoid
- Using the wrong connection (Q vs Q') between ripple stages. It decides up or down counting.
- Forgetting that the async clear method briefly shows state N.
- Treating a ripple counter as having a single propagation delay. It is n × t_pd.
- Mixing up ring (n states) and Johnson (2n states).
- Forgetting to initialise ring and Johnson counters, or to check that unused states lead back to valid ones.
- Assuming a MOD-N output always has a 50% duty cycle. It usually does not.
- Forgetting that cascaded moduli multiply, not add.
Likely quick-fire questions
- Why is a ripple counter slow? Each stage waits for the previous one, so delays add up to n × t_pd.
- How do you build a MOD-6 counter? Three flip-flops, truncated at 6 using a clear (async) or modified next-state logic (sync).
- Why does a synchronous counter run faster? All flip-flops change at once; only one flip-flop delay plus gate delay limits the clock.
- What makes a Johnson counter more efficient than a ring counter? It uses n flip-flops for 2n states.
- How do you divide a clock by 1000? Cascade three decade counters.
- Why do glitches appear in counters? Output bits change at slightly different times, creating brief false states.